Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2026052690-A1
Application number	US-202519367832-A
Country	US
Kind code	A1
Filing date	Oct 24, 2025
Priority date	Feb 23, 2023
Publication date	Feb 19, 2026
Grant date	—

Abstract

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a gate stack structure, a channel structure passing through the gate stack structure, and a memory layer between the channel structure and the gate stack structure. A channel layer or a channel pattern, which constitutes the channel structure, includes a structure having a corner or includes a filling type structure and a liner type structure.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first structure including a cell array structure and a first conductive bonding pad electrically connected to the cell array structure; a doped semiconductor structure including a first surface facing the first structure and a second surface facing opposite to the first surface; and a second structure including a second conductive bonding pad being in contact with the first conductive bonding pad and a peripheral circuit electrically connected to the second conductive bonding pad, wherein the cell array structure comprising:
a gate stack structure including conductive layers stacked over the first surface of the doped semiconductor structure;
a channel layer including a first portion extending along a sidewall of the gate stack structure, a second portion extending to the inside of the doped semiconductor structure from the first portion, and a third portion extending toward the second surface of the doped semiconductor structure from the second portion, the second portion of the channel layer includes a first corner adjacent to the gate stack structure and a second corner between the second surface of the doped semiconductor structure and the first corner; and
a memory layer disposed between the first portion of the channel layer and the sidewall of the gate stack structure.

2 . The semiconductor memory device of claim 1 , wherein the first structure disposed between the doped semiconductor structure and the second structure.

3 . The semiconductor memory device of claim 1 , wherein the gate stack structure disposed between the doped semiconductor and the second structure.

4 . The semiconductor memory device of claim 1 , wherein the second portion of the channel layer protrudes further laterally than the first and third portions of the channel layer.

5 . The semiconductor memory device of claim 1 , wherein a sidewall of the third portion of the channel layer is in contact with the doped semiconductor structure.

6 . The semiconductor memory device of claim 1 , wherein the doped semiconductor structure includes a first sidewall being in contact with the third portion of the channel layer and a second sidewall spaced apart from the third portion of the channel layer, and
wherein the first and second sidewalls of the doped semiconductor structure are aligned in a stacking direction of the conductive layers of the gate stack structure.

7 . The semiconductor memory device of claim 6 , further comprising an interposition layer disposed between the second sidewall the doped semiconductor structure and the third portion of the channel layer,
wherein the interposition layer includes the same material layers as the memory layer.

8 . The semiconductor memory device of claim 1 , wherein the conductive layers of the gate stack structure are spaced apart from each other and stacked along the first portion of the channel layer.

9 . A semiconductor memory device comprising:
a first structure including a cell array structure and a first conductive bonding pad electrically connected to the cell array structure; a doped semiconductor structure including a first surface facing the first structure and a second surface facing opposite to the first surface; and a second structure including a second conductive bonding pad being in contact with the first conductive bonding pad and a peripheral circuit electrically connected to the second conductive bonding pad, wherein the cell array structure comprising:
a gate stack structure including conductive layers stacked over the first surface of the doped semiconductor structure;
a channel structure disposed to penetrate the gate stack structure and including a channel layer, the channel layer including a first portion extending along a sidewall of the channel structure, a second portion extending to the inside of the doped semiconductor structure from the first portion, and a third portion extending toward the second surface of the doped semiconductor structure from the second portion, the channel layer including a first corner adjacent to the gate stack structure and a second corner adjacent to the third portion; and
a memory layer disposed between the first portion of the channel layer and the sidewall of the gate stack structure.

10 . The semiconductor memory device of claim 9 , wherein the first structure disposed between the doped semiconductor structure and the second structure.

11 . The semiconductor memory device of claim 9 , wherein the gate stack structure disposed between the doped semiconductor and the second structure.

12 . The semiconductor memory device of claim 9 , wherein the second portion of the channel layer protrudes further laterally than the first and third portions of the channel layer.

13 . The semiconductor memory device of claim 9 , wherein a sidewall of the third portion of the channel layer is in contact with the doped semiconductor structure.

14 . The semiconductor memory device of claim 13 , wherein the doped semiconductor structure includes a first doped semiconductor layer being in contact with a contact portion of the sidewall of the third portion of the channel layer and a second doped semiconductor layer spaced apart from the contact portion of the sidewall of the third portion of the channel layer.

15 . The semiconductor memory device of claim 14 , further comprising an interposition layer disposed between the doped semiconductor structure and the sidewall of the third portion of the channel layer,
wherein the interposition layer includes the same material layers as the memory layer.

16 . The semiconductor memory device of claim 14 , wherein each of the first and second portion of the channel layer includes a ring-shaped cross section, and
wherein the third portion of the channel layer includes a circular cross section.

17 . The semiconductor memory device of claim 9 , wherein the second corner is disposed between the third portion and the second portion of the channel layer.

18 . The semiconductor memory device of claim 9 , wherein the second portion of the channel layer includes the first corner and the second corner.

19 . The semiconductor memory device of claim 18 , wherein the second portion of the channel layer extends from the first corner to the second corner to form a convex sidewall that connects the first portion and the third portion of the channel layer.

20 . The semiconductor memory device of claim 9 ,
wherein the channel structure and the memory layer are formed in a channel hole, and wherein the channel hole includes a gate penetration portion in which the first portion of the channel layer is disposed, a middle portion in which the second portion of the channel layer is disposed, and an end portion in which the third portion of the channel layer is disposed.

21 . The semiconductor memory device of claim 20 , wherein the middle portion of the channel hole has a width greater than that of the gate penetration portion of the channel hole, with the difference in width defining a corner.

22 . The semiconductor memory device of claim 20 , wherein the middle portion of the channel hole has a width greater than that of the end portion of the channel hole, with the difference in width defining a corner.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Park In Su
• Jang Jung Shik

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title