Power chip package structure

Patent metadata

Field	Value
Publication number	US-2026047480-A1
Application number	US-202418929572-A
Country	US
Kind code	A1
Filing date	Oct 28, 2024
Priority date	Aug 9, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A power chip package structure includes a power chip, a first transmission member, and at least two second transmission members, an encapsulant, and a diamond-like carbon (DLC) layer. The first transmission member and the at least two second transmission members are connected to the power chip. The power chip, the first transmission member, and the at least two second transmission members are embedded in the encapsulant. The encapsulant has a layout surface that is coplanar with a first end surface of the first transmission member and a second end surface of each of the at least two second transmission members. The DLC layer is formed on the layout surface with terminals. The DLC layer surrounds the first end surface to jointly form a first solder-receiving slot, and the DLC layer surrounds each of the two second end surfaces to jointly form a second solder-receiving slot.

First claim

What is claimed is:

1 . A power chip package structure, comprising:
a power chip including:
a chip body having a first surface and a second surface that is opposite to the first surface;
a first bonding pad formed on the first surface; and
at least two second bonding pads formed on the second surface and spaced apart from each other;
a first transmission member connected to the first bonding pad, wherein the first transmission member has a first end surface that is arranged away from the first bonding pad; at least two second transmission members respectively connected to the at least two second bonding pads, wherein each of the at least two second transmission members has a second end surface that is arranged away from the corresponding second bonding pad; an encapsulant, wherein the power chip, the first transmission member, and the at least two second transmission members are embedded in the encapsulant, and wherein the encapsulant has a layout surface that is coplanar with the first end surface of the first transmission member and the second end surfaces of the two second transmission member; and a diamond-like carbon (DLC) layer formed on the layout surface, wherein the DLC layer surrounds the first end surface to jointly define a first solder-receiving slot, and the DLC layer surrounds each of the two second end surfaces to jointly define a second solder-receiving slot; wherein the first end surface is spaced apart from an adjacent one of the two second end surfaces by a clearance distance that is defined along the first solder-receiving slot, the corresponding second solder-receiving slot, and a part of an outer end surface of the DLC layer.

2 . The power chip package structure according to claim 1 , wherein the DLC layer covers an entirety of the layout surface of the encapsulant.

3 . The power chip package structure according to claim 1 , wherein the DLC layer covers a peripheral region of the first end surface having a width that is within a range from 5 μm to 100 μm, and the DLC layer covers a peripheral region of each of the two second end surfaces having a width that is within a range from 5 μm to 100 μm.

4 . The power chip package structure according to claim 1 , wherein a thickness of the DLC layer is within a range from 3 μm to 20 μm, and a resistivity of the DLC layer is greater than 10 10 ohm-cm.

5 . The power chip package structure according to claim 1 , wherein the encapsulant has an outer surface connected to a peripheral edge of the layout surface, and the power chip, the first transmission member, and the at least two second transmission members are located in a region surrounded by the outer surface of the encapsulant, wherein the power chip package structure further includes an electrical protection layer that is formed on the outer surface of the encapsulant and that is made of a DLC material, and wherein the electrical protection layer is not in contact with the DLC layer, and a resistivity of the electrical protection layer is less than a resistivity of the DLC layer.

6 . The power chip package structure according to claim 5 , wherein the resistivity of the electrical protection layer is less than 10 10 ohm-cm, and a resistivity of the DLC layer is greater than 10 10 ohm-cm.

7 . The power chip package structure according to claim 1 , wherein the first transmission member is a lead frame, one end of the lead frame has the first end surface, and another end of the lead frame is connected to the first bonding pad, and wherein each of the at least two second transmission members is a metal block, and the at least two second transmission members are respectively connected to the at least two second bonding pads.

8 . The power chip package structure according to claim 1 , further comprising a ceramic board embedded in the encapsulant, an inner metal layer formed on the ceramic board, and an extending metal block that is connected to one end of the inner metal layer, wherein the inner metal layer and the extending metal block are jointly defined as the first transmission member, the extending metal block has the first end surface, and another end of the extending metal block is connected to the first bonding pad, and wherein each of the at least two second transmission members is a metal block, and the at least two second transmission members are respectively connected to the at least two second bonding pads.

9 . The power chip package structure according to claim 8 , further comprising an outer metal layer, wherein the inner metal layer and the outer metal layer are respectively electrically bonded to two opposite surfaces of the ceramic board, and a surface of the outer metal layer arranged away from the inner metal layer is exposed from the encapsulant.

10 . The power chip package structure according to claim 1 , further comprising a plurality of conductive pastes, wherein the first transmission member is electrically bonded to the first bonding pad through one of the conductive pastes, and each of the at least two second transmission members is sintered to the corresponding second bonding pad through one of the conductive pastes.

11 . The power chip package structure according to claim 1 , wherein the first bonding pad is a drain pad, and the at least two second bonding pads are a source pad and a gate pad, respectively.

12 . A power chip package structure, comprising:
a power chip including:
a chip body having a first surface and a second surface that is opposite to the first surface;
a first bonding pad formed on the first surface; and
at least two second bonding pads formed on the second surface and spaced apart from each other;
a first transmission member connected to the first bonding pad, wherein the first transmission member has a first end surface that is arranged away from the first bonding pad; at least two second transmission members respectively connected to the at least two second bonding pads, wherein each of the at least two second transmission members has a second end surface that is arranged away from the corresponding second bonding pad; an encapsulant, wherein the power chip, the first transmission member, and the at least two second transmission members are embedded in the encapsulant, wherein the encapsulant has a layout surface and at least one slot that is recessed in the layout surface, and wherein a part of the first transmission member and a part of each of the at least two second transmission members are arranged in the at least one slot; and a diamond-like carbon (DLC) layer formed in the at least one slot and surrounding the part of the first transmission member and the part of each of the at least two second transmission members, wherein an outer end surface of the DLC layer is coplanar with the first end surface and the two second end surfaces; wherein the first end surface is spaced apart from an adjacent one of the two second end surfaces by a clearance distance that is defined along a part of the outer end surface of the DLC layer.

13 . The power chip package structure according to claim 12 , wherein the first end surface and the two second end surfaces are coplanar with the layout surface, a quantity of the at least one slot is three, and the three slots include:
a first slot surrounding the part of the first transmission member, wherein a part of the DLC layer filled in the first slot is defined as a first ring; and two second slots respectively surrounding the parts of the at least two second transmission members, wherein parts of the DLC layer respectively filled in the two second slots are each defined as a second ring, and wherein the first ring and the

Assignees

• Tong Hsing Electronic Industries Ltd

Inventors

• Hsieh Yu-Te
• Chiu Zzu-Chi
• Chen Yan-Wei

Classifications

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/641

  Dispositions of strap connectors · CPC title