Structures with through-substrate vias and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2026047415-A1
Application number	US-202519264574-A
Country	US
Kind code	A1
Filing date	Jul 9, 2025
Priority date	Dec 28, 2020
Publication date	Feb 12, 2026
Grant date	—

Abstract

A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.

First claim

1 . (canceled)

2 . A microelectronic structure comprising:
a bonding surface; a bulk semiconductor portion having a first side and a second side opposite the first side; a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side and extending to the bonding surface; and a dielectric layer having a first surface and a second surface opposite the first surface, the first surface disposed on the first side of the bulk semiconductor portion and extending to the via structure, the second surface comprising at least a portion of the bonding surface, wherein the second side of the bulk semiconductor portion comprises an active surface that includes circuitry, and wherein one or more metallization layers are over the active surface.

3 . The microelectronic structure of claim 2 , wherein a barrier dielectric layer intervenes between the dielectric layer and the bulk semiconductor portion but does not intervene between the dielectric layer and the via structure.

4 . The microelectronic structure of claim 2 , wherein the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the dielectric layer extending to the dielectric liner.

5 . The microelectronic structure of claim 2 , wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has first artifacts indicative of a first etching process and a second sidewall of the dielectric layer adjacent the via structure has second artifacts indicative of a second etching process different from the first etching process.

6 . The microelectronic structure of claim 5 , wherein the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

7 . The microelectronic structure of claim 6 , wherein the surface roughness profile of the second sidewall is smoother than the surface roughness profile of the first sidewall.

8 . The microelectronic structure of claim 2 , wherein the via structure has an exposed end surface that is recessed relative to the second surface of the dielectric layer, and the exposed end surface of the via structure and the second surface of the dielectric layer comprise planarized surfaces.

9 . The microelectronic structure of claim 2 , wherein the bonding surface comprises the second surface of the second dielectric layer and an exposed end surface of the via structure, and wherein the bonding surface is directly bonded to another element without an intervening adhesive along a bonding interface.

10 . The microelectronic structure of claim 2 , wherein the dielectric layer comprises a silicon oxynitride layer.

11 . A microelectronic structure comprising:
a first element comprising:
a bonding surface;
a bulk semiconductor portion having a first side and a second side opposite the first side;
a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side and extending to the bonding surface; and
a dielectric layer having a first surface and a second surface opposite the first surface, the first surface disposed on the first side of the bulk semiconductor portion and extending to the via structure, the second surface comprising at least a portion of the bonding surface; and
a second element directly bonded to the bonding surface of the first element without an intervening adhesive.

12 . The microelectronic structure of claim 11 , wherein the second side of the bulk semiconductor portion comprises an active surface that includes circuitry, and wherein one or more metallization layers are over the active surface.

13 . The microelectronic structure of claim 11 , wherein the bonding surface is hybrid bonded to the other element, such that the dielectric layer is directly bonded to a nonconductive region of the other element without an intervening adhesive along the bonding interface, and such that the via structure is directly bonded to a conductive region of the other element without an intervening adhesive along the bonding interface.

14 . The microelectronic structure of claim 11 , wherein a barrier dielectric layer intervenes between the dielectric layer and the bulk semiconductor portion but does not intervene between the dielectric layer and the via structure.

15 . The microelectronic structure of claim 11 , wherein the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the dielectric layer extending to the dielectric liner.

16 . The microelectronic structure of claim 11 , wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has first artifacts indicative of a first etching process and a second sidewall of the dielectric layer adjacent the via structure has second artifacts indicative of a second etching process different from the first etching process.

17 . The microelectronic structure of claim 16 , wherein the first and second artifacts have different surface roughness profiles along the first and second sidewalls.

18 . The microelectronic structure of claim 17 , wherein the surface roughness profile of the second sidewall is smoother than the surface roughness profile of the first sidewall.

19 . A microelectronic structure comprising:
a bonding surface; a bulk semiconductor portion having a first side and a second side opposite the first side; a via structure extending at least partially through the bulk semiconductor portion along a direction non-parallel to the first side and extending to the bonding surface; and a dielectric layer having a first surface and a second surface opposite the first surface, the first surface disposed over the first side of the bulk semiconductor portion and extending to the via structure, the second surface comprising at least a portion of the bonding surface.

20 . The microelectronic structure of claim 19 , wherein a barrier dielectric layer intervenes between the dielectric layer and the bulk semiconductor portion but does not intervene between the dielectric layer and the via structure.

21 . The microelectronic structure of claim 19 , wherein the via structure comprises a conductive via and a dielectric liner disposed around the conductive via, the dielectric layer extending to the dielectric liner.

22 . The microelectronic structure of claim 19 , wherein a first sidewall of the bulk semiconductor portion adjacent the via structure has a first surface roughness, and a second sidewall of the dielectric layer adjacent the via structure has a second surface roughness different from the first surface roughness.

23 . The microelectronic structure of claim 22 , wherein the second surface roughness is smoother than the first surface roughness.

24 . The microelectronic structure of claim 19 , wherein the dielectric layer comprises a silicon oxynitride layer.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Fountain Jr Gaius Gillman

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title