Data storage apparatus with improved write efficiency, operating method thereof, and memory controller therefor

Patent metadata

Field	Value
Publication number	US-2026044262-A1
Application number	US-202519007555-A
Country	US
Kind code	A1
Filing date	Jan 2, 2025
Priority date	Aug 6, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A data storage apparatus includes a memory device and a memory controller. The memory controller is configured to determine that at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus overlaps. The memory controller is configured to execute an overlap write mode in which deferring programming of data of an overlapping logical address.

First claim

What is claimed is:

1 . A data storage apparatus comprising:
a memory device; and a memory controller configured to
determine that at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus overlaps, and
execute, in response to a first write request including a first logical addresses received at a first timing, an overlap write mode in which data corresponding to a logical address, which non-overlaps a second logical addresses included in a second write request received subsequent to the first write request at a second timing, is programmed in the memory device while deferring programming data of an overlapping logical address.

2 . The data storage apparatus of claim 1 , wherein the memory controller is configured to determine whether the at least a portion of the logical addresses overlaps when each write request includes a plurality of logical addresses.

3 . The data storage apparatus of claim 1 , wherein the memory controller determines that the at least a portion of the logical addresses overlaps when a leading address of the second logical addresses is equal to or less than a last address of the first logical addresses.

4 . The data storage apparatus of claim 1 , wherein the memory controller is configured to enable and execute the overlap write mode when the at least a portion of the logical addresses overlaps, and disable the overlap write mode when a request other than the write requests is received from the external apparatus.

5 . The data storage apparatus of claim 4 , wherein the request other than the write requests includes at least one of a read command, a manager command of the external apparatus, a management command corresponding to power loss of the external apparatus, a reset command, and a command related to error processing.

6 . The data storage apparatus of claim 1 , wherein, when a read command is received from the external apparatus while executing the overlap write mode, the memory controller is configured to program programming-deferred data, and execute the read command.

7 . A memory controller comprising:
an overlap write manager configured to: determine whether at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus overlaps; and defer, based on a first write request including a first logical addresses received at a first timing and a second logical addresses included in a second write request received subsequent to the first write request at a second timing, writing data corresponding to the first logical addresses of the first write request, the data to be updated.

8 . The memory controller of claim 7 , wherein, when a read command is received from the external apparatus, the memory controller is configured to program writing-deferred data, and execute the read command.

9 . An operating method of a data storage apparatus, the operating method comprising:
determining whether at least a portion of logical addresses included in adjacent write requests in a sequence of write requests continuously received from an external apparatus, overlaps; executing an overlap write mode in response to a determination that the at least a portion of the logical addresses overlaps; during the overlap write mode, controlling, in response to a first write request including a first logical addresses received at the first timing, data corresponding to a logical address which non-overlaps a second logical addresses included in a second write request received subsequent to the first write request at a second timing, to be programmed while deferring programming data corresponding to a logical address of the first logical addresses, which overlaps the second logical addresses.

10 . The operating method of claim 9 , wherein determining whether or not the at least a portion of the logical addresses overlaps when one each write request includes a plurality of logical addresses.

11 . The operating method of claim 9 , wherein the determining comprises determining whether a leading address of the second logical addresses is equal to or less than a last address of the first logical addresses.

12 . The operating method of claim 9 , wherein executing the overlap write mode comprises:
enabling and executing the overlap write mode in response to the determination that the at least a portion of the logical addresses overlaps; and disabling the overlap write mode in response to a request other than the write requests received from the external apparatus.

13 . The operating method of claim 12 , wherein the request other than the write request includes at least one of a read command, a manager command of the external apparatus, a management command corresponding to power loss of the external apparatus, a reset command, and a command related to error processing.

14 . The operating method of claim 9 , further comprising:
receiving a read command from the external apparatus while executing the overlap write mode; programing programming-deferred data; and executing the read command.

Assignees

• Sk Hynix Inc

Inventors

• Kim Ki Tae

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title