Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order

Patent metadata

Field	Value
Publication number	US-10474390-B1
Application number	US-201715586723-A
Country	US
Kind code	B1
Filing date	May 4, 2017
Priority date	May 4, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory.

First claim

What is claimed is:

1. A circuit, comprising:
an address generator configured to generate a write address signal and a read address signal, wherein the write address signal has a first delay relative to the read address signal;
a write data delay circuit configured to generate a delayed write data signal using a write data signal based on the first delay; and
a memory configured to:
receive, from the write address signal, a first plurality of write addresses including a first plurality of addresses of the memory in a first order;
write, to the first plurality of write addresses, a first plurality of data words of the delayed write data signal during a first time period;
receive, from the read address signal, a first plurality of read addresses including the first plurality of addresses of the memory in a second order; and
read, from the first plurality of read addresses, the first plurality of data words during a second time period,
wherein the first delay is configured to eliminate an overlapping of read and write addresses during each of one or more clock cycles of a first overlap time period of the first and second time periods.

2. The circuit of claim 1 , wherein the memory is further configured to:
receive, from the write address signal, a second plurality of write addresses including the first plurality of addresses in the second order; and
write a second plurality of data words to the second plurality of write addresses during a third time period, wherein a second overlap time period of the second and third time periods includes one or more clock cycles.

3. The circuit of claim 1 , wherein the address generator is configured to generate the write address signal and read address signal using a first address signal, and wherein the address generator includes:
a first delay circuit configured to apply the first delay to the first address signal to generate the write address signal.

4. The circuit of claim 2 ,
wherein the first delay is configured to eliminate an overlapping of read and write addresses during each clock cycle of the second overlap time period.

5. The circuit of claim 4 , further comprising:
a third delay circuit configured to apply the first delay to a write enable signal synchronized with the write data signal to generate a delayed write enable signal;
wherein the memory is configured to enable write operations to the memory based on the delayed write enable signal.

6. The circuit of claim 1 , wherein the memory is a read-before-write memory.

7. The circuit of claim 1 , wherein the memory is a write-before-read memory.

8. The circuit of claim 1 , wherein the address generator includes:
a write address generator configured to generate a first address signal;
a read address generator configured to generate the read address signal synchronized with the first address signal; and
a first delay circuit configured to apply the first delay to the first address signal to generate the write address signal.

9. The circuit of claim 8 , wherein the first plurality of read addresses include cyclic prefix addresses.

10. The circuit of claim 1 , wherein the first order is one of a natural order and a modified order, and the second order is the other of the natural order and the modified order; and
wherein the modified order is one of a bit-reversed order and a digit-reversed order.

11. A method, comprising:
providing, to a memory, a write address signal and a read address signal, wherein the write address signal has a first delay relative to the read address signal;
generate a delayed write data signal using a write data signal based on the first delay;
writing, to the memory, a first plurality of data words of the delayed write data signal at a plurality of addresses according to a first order based on the write address signal during a first time period including a first clock cycle, wherein the writing of the first plurality of data words includes:
during the first clock cycle, writing a first data word of the first plurality of data words at a first address of the plurality of addresses; and

reading, from the memory, the first plurality of data words at the plurality of addresses according to a second order based on the write address signal during a second time period including the first clock cycle, wherein the reading of the first plurality of data words includes:
during the first clock cycle, reading a second data word of the first plurality of data words at a second address of the plurality of addresses, wherein the second address is different from the first address.

12. The method of claim 11 , further comprising:
generating the read address signal and write address signal based on a first address signal.

13. The method of claim 12 , further comprising:
writing, to the memory, a second plurality of data words at the plurality of addresses according to the second order based on the write address signal during a third time period including a second clock cycle; and
reading, from the memory, the second plurality of data words at the plurality of addresses according to the first order based on the read address signal during a fourth time period including the second clock cycle.

14. The method of claim 13 , wherein the writing of the second plurality of data words includes:
during the second clock cycle, writing a third data word of the second plurality of data words at the second address of the plurality of addresses; and
wherein the reading of the second plurality of data words includes:
during the second clock cycle, reading a fourth data word of the first plurality of data words at a third address of the plurality of addresses,
wherein the third address is different from the second address.

15. The method of claim 11 , wherein the first order is one of a natural order and a modified order, and the second order is the other of the natural order and the modified order.

16. The method of claim 15 , wherein the modified order is one of a bit-reversed order and a digit-reversed order.

17. The method of claim 11 , further comprising:
processing the first plurality of data words according to a Fourier transform function.

18. The method of claim 11 , further comprising:
processing the first plurality of data words according to a polar error-correcting code.

19. The method of claim 11 , wherein during the first clock cycle, the writing of the first data word is performed prior to the reading of the second data word.

20. The method of claim 11 , wherein during the first clock cycle, the writing of the first data word is performed after the reading of the second data word.

Assignees

• Xilinx Inc

Inventors

• Whyte Andrew M

Classifications

• H03K19/1776

  for memories · CPC title

• G11C8/04

  using a sequential addressing device, e.g. shift register, counter · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title