Direct-bonded optoelectronic interconnect for high-density integrated photonics

Patent metadata

Field	Value
Publication number	US-2026041012-A1
Application number	US-202519353456-A
Country	US
Kind code	A1
Filing date	Oct 8, 2025
Priority date	Dec 15, 2017
Publication date	Feb 5, 2026
Grant date	—

Abstract

Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays. The adhesive-free dielectric-to-dielectric direct bonding and solder-free metal-to-metal direct bonding creates high-density electrical interconnects on the same bonding interface as the bonded optical interconnect. Known-good-dies may be used, which is not possible conventionally, and photolithography over their top surfaces can scale to high density.

First claim

What is claimed is:

1 . A structure, comprising:
a first die comprising a first surface having a first plurality of electrical contacts and a first dielectric region, wherein the first dielectric region includes a first optical window providing an optical path for communication with the first die; and a second die comprising a second surface having a second plurality of electrical contacts and a second dielectric region, wherein the first and second surfaces are directly bonded such that the first and second pluralities of electrical contacts are directly bonded and the first and second dielectric regions are directly bonded, and wherein the first surface is larger than the second surface.

2 . The structure of claim 1 , wherein the first die includes a silicon-on-insulator substrate.

3 . The structure of claim 1 , wherein the first die comprises a waveguide and photonic circuits, the waveguide to couple light into the photonic circuits.

4 . The structure of claim 1 , further comprising a substrate disposed over the second die.

5 . The structure of claim 1 , further comprising a substrate from a reconstituted wafer, wherein the second die is at least partially embedded in the substrate.

6 . The structure of claim 1 , wherein the optical path comprises a dielectric material to reduce reflection loss.

7 . A structure, comprising:
a first die comprising a first surface having a first region with a first plurality of electrical contacts and a second region with a first optical area; a second die or wafer disposed over the first die or wafer, the second die or wafer comprising a second surface having a second plurality of electrical contacts, wherein the first surface and the second surface are hybrid bonded, wherein the first plurality of electrical contacts is directly bonded to the second plurality of electrical contacts; a first substrate disposed over the second die or wafer; and an optical pathway between and including at least the first optical area and at least a portion of the substrate, wherein the first region is external to the second region such that the first plurality of electrical contacts does not interfere with the optical pathway.

8 . The structure of claim 7 , wherein the optical pathway comprises a dielectric material.

9 . The structure of claim 7 , wherein the optical pathway is a vertical optical pathway.

10 . The structure of claim 7 , wherein the first die comprises a silicon-on-insulator substrate.

11 . The structure of claim 7 , wherein the first die comprises a grating surface.

12 . The structure of claim 11 , wherein the first die comprises a waveguide, wherein the grating surface couples light into the waveguide.

13 . The structure of claim 7 , wherein the second die or wafer comprises a second substrate from a reconstituted wafer.

14 . A structure, comprising:
a first element comprising optoelectronic circuitry, and first conductive contacts and a first optical window at a first surface of the first element; a second element comprising a die having second conductive contacts, and a second optical window at a second surface of the second element; and an optical path extending between the first element and the second element, wherein the optical path includes the first optical window and the second optical window, wherein the first optical window directly contacts the second optical window.

15 . The structure of claim 14 , wherein the optical path comprises a dielectric material to reduce reflection loss.

16 . The structure of claim 14 , wherein the optical path comprises a reflective layer.

17 . The structure of claim 14 , wherein the first conductive contacts are directly bonded to the second conductive contacts.

18 . The structure of claim 14 , wherein the first element comprises a silicon-on-insulator substrate.

19 . The structure of claim 14 , wherein the first element comprises a waveguide and a grating coupler, the grating coupler to couple light into the waveguide.

20 . The structure of claim 14 , wherein the first conductive contacts are located at a first region of the first surface, wherein the first optical window is located at a second region of the first surface, the first region different than the second region, and wherein the second conductive contacts are located at a third region of the second surface, wherein the second optical window is located at a fourth region of the second surface, the third region different than the fourth region.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Wang Liang
• Katkar Rajesh

Classifications

• H10H20/0364

  of interconnections · CPC title

• H10H20/036

  of packages · CPC title

• H01L2924/12044

  Electricity · mapped topic

• H01L2924/12041

  Electricity · mapped topic

• H01L2224/83896

  Electricity · mapped topic