Semiconductor device packages

Patent metadata

Field	Value
Publication number	US-2026040980-A1
Application number	US-202519358734-A
Country	US
Kind code	A1
Filing date	Oct 15, 2025
Priority date	Nov 11, 2021
Publication date	Feb 5, 2026
Grant date	—

Abstract

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

First claim

What is claimed is:

1 . A method comprising:
disposing a substrate on a first insulating film, the substrate including one or more features formed therein; disposing one or more semiconductor die between the one or more features of the substrate; disposing a protective film over the substrate and the one or more semiconductor die; exposing the substrate to a first lamination process; disposing a second insulating film over the substrate; exposing the substrate to a second lamination process; curing the second insulating film; and forming one or more through-assembly vias extending through the substrate and the insulating film.

2 . The method of claim 1 , wherein the substrate comprises silicon.

3 . The method of claim 1 , wherein the first insulating film comprises a polymer-based dielectric material.

4 . The method of claim 1 , wherein the at least one via is formed by laser ablation.

5 . The method of claim 1 , further comprising forming contact holes in the second insulating film to expose electrical contacts of the one or more semiconductor die.

6 . The method of claim 1 , wherein the first insulating film or the second insulating film comprises a ceramic-filler-containing epoxy resin.

7 . The method of claim 1 , wherein the one or more semiconductor die comprises a power delivery network on a back side and signal contacts on a front side.

8 . A method comprising:
providing a substrate having at least one feature formed therein; placing at least one semiconductor die in association with the at least one feature, the semiconductor die having electrical contacts disposed on opposing major surfaces; applying at least one insulating material over the substrate and the at least one semiconductor die; laminating the substrate and the at least one semiconductor die with the insulating material; curing the insulating material; and forming at least one opening extending through the substrate and the insulating material to expose the electrical contacts on both major surfaces of the semiconductor die.

9 . The method of claim 8 , wherein the at least one feature comprises a cavity.

10 . The method of claim 8 , wherein the at least one opening is filled with a conductive material.

11 . The method of claim 8 , wherein the insulating material comprises a ceramic-filler-containing epoxy resin.

12 . A method comprising:
forming a cavity and a plurality of vias in a substrate; disposing a semiconductor die within the cavity, the semiconductor die having electrical contacts on a first side and a second side; applying an insulating layer over the substrate and the semiconductor die; laminating the substrate with the insulating layer; curing the insulating layer; and forming an opening through the substrate and the insulating layer to expose the electrical contacts on both the first side and the second side of the semiconductor die.

13 . The method of claim 12 , wherein the substrate comprises monocrystalline silicon.

14 . The method of claim 12 , wherein the insulating layer comprises silicon dioxide.

15 . The method of claim 12 , further comprising forming a metal cladding layer on at least a portion of the substrate.

16 . The method of claim 12 , wherein the plurality of vias are arranged in at least two rows along an edge of the cavity.

17 . The method of claim 12 , further comprising coupling the substrate to a carrier plate during formation of the cavity and the plurality of vias.

18 . The method of claim 12 , wherein the insulating layer has a thickness between about 10 μm and about 120 μm.

19 . The method of claim 12 , wherein a metal cladding layer comprises nickel.

20 . The method of claim 12 , wherein the plurality of vias are formed by drilling.

Assignees

• Applied Materials Inc

Inventors

• Verhaverbeke Steven
• Chen Han-Wen

Classifications

• H01L2924/3511

  Electricity · mapped topic

• H01L2924/1436

  Electricity · mapped topic

• H01L2224/16235

  Electricity · mapped topic

• H01L2224/08235

  Electricity · mapped topic

• H01L24/16

  Electricity · mapped topic