Semiconductor memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2026038535-A1
Application number	US-202519053170-A
Country	US
Kind code	A1
Filing date	Feb 13, 2025
Priority date	Aug 1, 2024
Publication date	Feb 5, 2026
Grant date	—

Abstract

A semiconductor memory device includes a substrate including a cell array region and an extension region, gate electrodes on the substrate, a channel structure on the cell array region, and an insulating pattern. The gate electrodes are alternately stacked in a first direction, providing a staircase structure on the extension region. The channel structure penetrates the gate electrodes. A first through via penetrates first and second gate electrodes. The first through via, disposed between the first gate electrode and the substrate, is connected to the first gate electrode. The insulating pattern includes: an insulating structure; a liner insulating layer; and a capping pattern disposed between the insulating structure and a sidewall of the first through via. A width of a capping layer of the capping pattern decreases as a distance from the first through via increases.

First claim

1 . A semiconductor memory device comprising:
a substrate including a cell array region and an extension region; a plurality of gate electrodes on the substrate, wherein the plurality of gate electrodes are alternately stacked in a first direction perpendicular to an upper surface of the substrate, and the plurality of gate electrodes provide a staircase structure on the extension region; a channel structure on the cell array region, wherein the channel structure extends through the plurality of gate electrodes in the first direction; a first through via on the extension region, wherein the first through via extends through a first gate electrode of the plurality of gate electrodes and a second gate electrode of the plurality of gate electrodes, wherein the plurality of gate electrodes are between the first gate electrode and the substrate, and wherein the first through via is connected to the first gate electrode; and an insulating pattern between the second gate electrode and a sidewall of the first through via, wherein the insulating pattern includes
an insulating structure on a sidewall of the second gate electrode,
a liner insulating layer on an upper surface of the insulating structure, and
a capping pattern between the insulating structure and the sidewall of the first through via,
wherein the insulating structure includes a first insulating layer and a second insulating layer surrounding the first insulating layer, wherein the capping pattern includes a first capping layer disposed on the insulating structure, and a second capping layer between the first capping layer and the sidewall of the first through via, and wherein a width of the second capping layer in the first direction decreases as a distance from the first through via increases.

2 . The semiconductor memory device according to claim 1 , wherein the first capping layer is in contact with the first insulating layer and the second insulating layer.

3 . The semiconductor memory device according to claim 1 , wherein the second capping layer includes a concave curved surface in contact with the first capping layer.

4 . The semiconductor memory device according to claim 1 , wherein the first capping layer includes a convex curved surface protruding toward the second insulating layer.

5 . The semiconductor memory device according to claim 1 , wherein the first capping layer includes a material different from that of the second capping layer.

6 . The semiconductor memory device according to claim 1 , wherein there is a first void in the first insulating layer.

7 . The semiconductor memory device according to claim 1 , wherein there is a second void in the first capping layer.

8 . The semiconductor memory device according to claim 1 , wherein the liner insulating layer is elongated in a second direction different from the first direction and covers an upper surface of the capping pattern.

9 . The semiconductor memory device according to claim 1 , wherein the first through via includes a conductive pillar extending in the first direction and a barrier conductive film surrounding the conductive pillar, and
wherein the conductive pillar includes a connection portion protruding toward the first gate electrode.

10 . The semiconductor memory device according to claim 1 , wherein the first gate electrode includes a first filling conductive layer and a first liner dielectric layer surrounding the first filling conductive layer, and
wherein the first filling conductive layer and the first liner dielectric layer are in contact with the first through via.

11 . The semiconductor memory device according to claim 1 , wherein the second gate electrode includes a second filling conductive layer and a second liner dielectric layer surrounding the second filling conductive layer, and
wherein the second liner dielectric layer is in contact with the liner insulating layer and the second insulating layer.

12 . The semiconductor memory device according to claim 1 , wherein a sidewall of the second gate electrode has a concave shape.

13 . A semiconductor memory device comprising:
a substrate including a cell array region and an extension region; a mold structure on the substrate, wherein the mold structure includes a plurality of gate electrodes alternately stacked with a plurality of mold insulating layers in a first direction perpendicular to an upper surface of the substrate, and the plurality of gate electrodes include a pad portion disposed in a staircase structure on the extension region; a channel structure on the cell array region, wherein the channel structure extends through the plurality of gate electrodes in the first direction; a first through via on the extension region, wherein the first through via extends through a pad portion of a first gate electrode of the plurality of gate electrodes and through a second gate electrode of the plurality of gate electrodes, wherein the second gate electrode is between the first gate electrode and the substrate, and wherein the first through via is electrically connected to the pad portion of the first gate electrode; and an insulating pattern between the second gate electrode and the first through via, wherein the insulating pattern surrounds a portion of a sidewall of the first through via, wherein the insulating pattern includes
an insulating structure including a first insulating layer and a second insulating layer surrounding three surfaces of the first insulating layer, and
a capping pattern between the insulating structure and the sidewall of the first through via,
wherein the capping pattern includes a first capping layer covering a first side of an insulating structure defined by a side surface of the first insulating layer and a side surface of the second insulating layer, and includes a second capping layer between the first capping layer and the sidewall of the first through via, and wherein a width of the second capping layer in the first direction decreases as a distance from the first through via increases.

14 . The semiconductor memory device according to claim 13 , wherein the insulating structure includes the first side and a second side facing the first side in a second direction different from the first direction, and
wherein the second side of the insulating structure is in contact with the second gate electrode.

15 . The semiconductor memory device according to claim 13 , wherein a thickness of the pad portion of the first gate electrode is greater than a thickness of a plate of the first gate electrode.

16 . The semiconductor memory device according to claim 13 , further comprising:
a first liner insulating layer on an upper surface of the insulating pattern and on an upper surface of the capping pattern; and a second liner insulating layer on a lower surface of the insulating pattern and on a lower surface of the capping pattern.

17 . The semiconductor memory device according to claim 16 , wherein the second capping layer covers at least a portion of the sidewall of the first through via exposed between the first liner insulating layer and the second liner insulating layer.

18 . The semiconductor memory device according to claim 13 , further comprising a peripheral circuit structure on a lower surface of the substrate, where the lower surface faces the upper surface of the substrate,
wherein the first through via extends through the substrate and is connected to the peripheral circuit structure.

19 . The semiconductor memory device according to claim 13 , wherein the f

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyunho
• Kim Eunhyun
• Kim Hyung Joon

Classifications

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H01L2924/1438

  Electricity · mapped topic

• H01L2225/06541

  Electricity · mapped topic

• H01L2225/06524

  Electricity · mapped topic

• H01L2224/32225

  Electricity · mapped topic