Multi-step etching in memory architectures

Patent metadata

Field	Value
Publication number	US-2026033302-A1
Application number	US-202519272889-A
Country	US
Kind code	A1
Filing date	Jul 17, 2025
Priority date	Jul 29, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

Methods, systems, and devices for multi-step etching in memory architectures are described. A semiconductor device may be formed based on multiple etching operations. A first set of cavities may be etched through one or more materials prior to formation of conductive materials in the semiconductor device. Each first cavity may be etched through at least a portion of a first channel and a second channel of a set of multiple channels of the semiconductor device. After a formation of the conductive materials, one or more second cavities may be etched through a portion of the first set of oxide filled cavities and a portion of the conductive materials. The one or more second cavities may complete a division of the semiconductor device into multiple subblocks.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of channels; a plurality of word lines associated with the plurality of channels; a plurality of first oxide materials, each first oxide material formed through at least a portion of a first channel and a second channel of the plurality of channels; and one or more second oxide materials formed through at least a portion of the plurality of first oxide materials and the plurality of word lines, wherein the one or more second oxide materials divide the plurality of channels into subblocks, the subblocks being electrically isolated from each other based at least in part on the plurality of first oxide materials and the one or more second oxide materials.

2 . The semiconductor device of claim 1 , wherein each channel of the plurality of channels comprises:
a first cylinder formed of a nitride material; a second cylinder formed of a polysilicon material, the second cylinder surrounded by an oxide material and formed within the first cylinder; and a plug formed of the polysilicon material at an end of the first cylinder and the second cylinder.

3 . The semiconductor device of claim 2 , wherein, for the first channel and the second channel, a first edge of the first cylinder extends beyond a second edge of the second cylinder, a gap between the first edge and the second edge is filled with a second oxide material associated with the plurality of first oxide materials.

4 . The semiconductor device of claim 1 , wherein the plurality of first oxide materials and the one or more second oxide materials are formed at a first depth that is less than a second depth associated with the plurality of channels.

5 . The semiconductor device of claim 1 , wherein the one or more second oxide materials comprise:
a plurality of second oxide materials in between each of the plurality of first oxide materials to divide the plurality of channels, wherein the subblocks are electrically isolated from each other based at least in part on the plurality of second oxide materials.

6 . The semiconductor device of claim 1 , wherein the plurality of first oxide materials and the one or more second oxide materials are formed along a boundary between two or more subblocks of the semiconductor device.

7 . The semiconductor device of claim 1 , wherein each channel of the plurality of channels is associated with a plurality of memory cells formed along each channel.

8 . The semiconductor device of claim 1 , wherein the plurality of channels corresponds to a plurality of not-AND (NAND) channels.

9 . A method of manufacturing a semiconductor device, comprising:
etching a plurality of first cavities through a stack of materials comprising layers of nitride materials and oxide materials, a cavity of the plurality of first cavities extending through at least a portion of a first channel and a second channel of the semiconductor device; depositing an oxide material in the plurality of first cavities based at least in part on etching the plurality of first cavities; replacing, based at least in part on depositing the oxide material, the nitride materials with a conductive material to form a plurality of word lines associated with a plurality of channels of the semiconductor device including the first channel and the second channel; and etching, after replacing the nitride materials, one or more second cavities through at least a portion of the oxide material and the stack of materials to divide the plurality of channels into subblocks, wherein the subblocks are electrically isolated from each other based at least in part on etching the plurality of first cavities and etching the one or more second cavities.

10 . The method of claim 9 , wherein replacing the nitride materials comprises:
replacing the nitride materials with the conductive material for at least two subblocks of the semiconductor device based at least in part on oxide materials that remain between each cavity of the plurality of first cavities after etching the plurality of first cavities.

11 . The method of claim 9 , wherein each channel of the plurality of channels comprises:
a first cylinder formed of a nitride material; a second cylinder formed of a polysilicon material, the second cylinder surrounded by the oxide materials and formed within a cavity of the first cylinder; and a plug formed of the polysilicon material at an end of the first cylinder and the second cylinder.

12 . The method of claim 11 , wherein each channel of the plurality of channels is associated with a plurality of memory cells along each channel.

13 . The method of claim 11 , further comprising:
removing, for each channel of the plurality of channels, a portion of the second cylinder prior to depositing the oxide material.

14 . The method of claim 9 , further comprising:
depositing, prior to depositing the oxide material, a material in the plurality of first cavities to insulate an exposed face of each respective first channel and second channel from the oxide material.

15 . The method of claim 9 , wherein etching the one or more second cavities comprises:
etching a plurality of second cavities in between each of the plurality of first cavities to divide the plurality of channels, wherein the subblocks are electrically isolated from each other based at least in part on the plurality of second cavities.

16 . The method of claim 9 , wherein the plurality of first cavities and the one or more second cavities are etched along a boundary between two or more subblocks of the semiconductor device.

17 . A product formed by a process of:
etching a plurality of first cavities through a stack of materials comprising layers of nitride materials and oxide materials, a cavity of the plurality of first cavities extending through at least a portion of a first channel and a second channel of the product; depositing an oxide material in the plurality of first cavities based at least in part on etching the plurality of first cavities; replacing, based at least in part on depositing the oxide material, the nitride materials with a conductive material to form a plurality of word lines associated with a plurality of channels of the product including the first channel and the second channel; and etching, after replacing the nitride materials, one or more second cavities through at least a portion of the oxide material and the stack of materials to divide the plurality of channels into subblocks, wherein the subblocks are electrically isolated from each other based at least in part on etching the plurality of first cavities and etching the one or more second cavities.

18 . The product of claim 17 , wherein replacing the nitride materials comprises:
replacing the nitride materials with the conductive material for at least two subblocks of the product based at least in part on oxide materials that remain between each cavity of the plurality of first cavities after etching the plurality of first cavities.

19 . The product of claim 17 , the process further comprising:
depositing, prior to depositing the oxide material, a material in the plurality of first cavities to insulate an exposed face of each respective first channel and second channel from the oxide material.

20 . The product of claim 17 , wherein etching the one or more second cavities comprises:
etching a plurality of second cavities in between each of the plurality of first cavities to divide the plurality of channels, wherein the subblocks are ele

Assignees

• Micron Technology Inc

Inventors

• Hill Richard J
• Heineck Lars P
• Fukuzumi Yoshiaki

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H01L21/76224 Primary

  Electricity · mapped topic

• H10B12/02

  for one transistor one-capacitor [1T-1C] memory cells · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title