Integrated circuit device

Patent metadata

Field	Value
Publication number	US-2026032983-A1
Application number	US-202519023507-A
Country	US
Kind code	A1
Filing date	Jan 16, 2025
Priority date	Jul 29, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

An integrated circuit device includes a substrate having a word line trench formed therein, a gate insulating film covering an inner surface of the word line trench, a first gate pattern filling a lower region of the word line trench on the gate insulating film, an interface barrier film disposed on the first gate pattern, an intermediate insulating film covering the interface barrier film and a side surface of the gate insulating film, the side surface being higher than the upper surface of the interface barrier film relative to a lower surface of the substrate, a second gate pattern filling a middle region of the word line trench on the intermediate insulating film, an insulating capping pattern filling an upper region of the word line trench on the second gate pattern, and an oxide film covering a lower surface and side surfaces of the insulating capping pattern.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a substrate having a word line trench formed therein; a gate insulating film covering an inner surface of the word line trench; a first gate pattern filling a lower region of the word line trench on the gate insulating film; an interface barrier film disposed on the first gate pattern; an intermediate insulating film covering an upper surface of the interface barrier film and a side surface of the gate insulating film, the side surface of the gate insulating film being higher than the upper surface of the interface barrier film relative to a lower surface of the substrate; a second gate pattern filling a middle region of the word line trench on the intermediate insulating film; an insulating capping pattern filling an upper region of the word line trench on the second gate pattern; and an oxide film covering a lower surface and side surfaces of the insulating capping pattern.

2 . The integrated circuit device of claim 1 , wherein the intermediate insulating film comprises a horizontal extension portion arranged between the upper surface of the interface barrier film and a lower surface of the second gate pattern, and a vertical extension portion arranged on the gate insulating film to be in contact with side surfaces of the second gate pattern, and
the vertical extension portion extends from the upper surface of the interface barrier film to an upper portion of the word line trench, and upper surfaces of the vertical extension portion are disposed on the same plane as an upper surface of the insulating capping pattern.

3 . The integrated circuit device of claim 1 , wherein the intermediate insulating film comprises a horizontal extension portion arranged between the upper surface of the interface barrier film and a lower surface of the second gate pattern, and a vertical extension portion arranged on the gate insulating film to be in contact with side surfaces of the second gate pattern, and
upper surfaces of the vertical extension portion are arranged on a same plane as an upper surface of the second gate pattern.

4 . The integrated circuit device of claim 1 , wherein the oxide film comprises a first portion arranged between the upper surface of the second gate pattern and the lower surface of the insulating capping pattern, and a second portion extending vertically along side surfaces of the insulating capping pattern, and
an upper surface of the second portion is arranged on a same plane as the upper surface of the insulating capping pattern.

5 . The integrated circuit device of claim 1 , wherein the intermediate insulating film comprises ZnO, Al 2 O 3 , or TiO 2 .

6 . The integrated circuit device of claim 1 , wherein the intermediate insulating film is conformally formed on the interface barrier film and the gate insulating film, and
a thickness of the intermediate insulating film is between 5 Å and 30 Å.

7 . The integrated circuit device of claim 1 , wherein a thickness of the oxide film is between 5 Å and 40 Å.

8 . The integrated circuit device of claim 1 , wherein the first gate pattern comprises a metal or a conductive metal nitride, and
the second gate pattern comprises polysilicon.

9 . The integrated circuit device of claim 1 , wherein the interface barrier film comprises a nitride of a metal material included in the first gate pattern.

10 . The integrated circuit device of claim 1 , wherein the oxide film comprises silicon oxide.

11 . An integrated circuit device comprising:
a substrate having a word line trench formed therein; a gate insulating film covering an inner surface of the word line trench; a first gate pattern filling a lower region of the word line trench on the gate insulating film; an interface barrier film disposed on the first gate pattern; an intermediate insulating film covering an upper surface of the interface barrier film and a side surface of the gate insulating film, the side surface of the gate insulating film being higher than the upper surface of the interface barrier film relative to a lower surface of the substrate; a second gate pattern filling a middle region of the word line trench on the intermediate insulating film; an insulating capping pattern filling an upper region of the word line trench on the second gate pattern; and an oxide film disposed between the insulating capping pattern and the second gate pattern.

12 . The integrated circuit device of claim 11 , wherein the intermediate insulating film comprises a horizontal extension portion arranged between the upper surface of the interface barrier film and a lower surface of the second gate pattern, and a vertical extension portion arranged on the gate insulating film to be in contact with side surfaces of the second gate pattern, and
the vertical extension portion extend from the upper surface of the interface barrier film to an upper portion of the word line trench, and upper surfaces of the vertical extension portion are disposed on the same plane as the upper surface of the insulating capping pattern.

13 . The integrated circuit device of claim 11 , wherein the intermediate insulating film comprises a horizontal extension portion arranged between the upper surface of the interface barrier film and a lower surface of the second gate pattern, and a vertical extension portion arranged on the gate insulating film to be in contact with side surfaces of the second gate pattern, and
upper surfaces of the vertical extension portion are arranged on a same plane as an upper surface of the second gate pattern.

14 . The integrated circuit device of claim 11 , wherein the intermediate insulating film comprises ZnO, Al 2 O 3 , or TiO 2 .

15 . The integrated circuit device of claim 11 , wherein the intermediate insulating film is conformally formed on the interface barrier film and the gate insulating film, and
a thickness of the intermediate insulating film is between 5 Å and 30 Å.

16 . The integrated circuit device of claim 11 , wherein a thickness of the oxide film is 5 Å between 40 Å.

17 . The integrated circuit device of claim 11 , wherein the first gate pattern comprises a metal or a conductive metal nitride, and
the second gate pattern comprises polysilicon.

18 . The integrated circuit device of claim 11 , wherein the interface barrier film comprises a nitride of a metal material included in the first gate pattern.

19 . The integrated circuit device of claim 11 , wherein the oxide film comprises silicon oxide.

20 . An integrated circuit device comprising:
a substrate having a word line trench formed therein; a gate insulating film covering an inner surface of the word line trench; a first gate pattern filling a lower region of the word line trench on the gate insulating film; an interface barrier film disposed on the first gate pattern; an intermediate insulating film covering an upper surface of the interface barrier film and a side surface of the gate insulating film, the side surface of the gate insulating film being higher than the upper surface of the interface barrier film relative to a lower surface of the substrate; a second gate pattern filling a middle region of the word line trench on the intermediate insulating film; an insulating capping pattern filling an upper region of the word line trench on the second gate pattern; an oxide film covering a lower surface and side surfaces of the insulating capping pattern; and a pair of source/drain regions formed outside

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Geon-Beom
• Kim Doyun
• Lee Jongwon
• Rim Taiuk
• Jo Soyoung
• Chae Kyosuk

Classifications

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H10B12/488 Primary

  Word lines · CPC title

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title