Memory device including control gates having partial dielectric liners

Patent metadata

Field	Value
Publication number	US-2026032913-A1
Application number	US-202519283806-A
Country	US
Kind code	A1
Filing date	Jul 29, 2025
Priority date	Jul 29, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: first memory cells and an associated first control gate located on a first level of the apparatus; second memory cells and an associated second control gate located on a second level of the apparatus; a level of dielectric material between the first and second control gates; the second control gate including a conductive material, and a first dielectric liner and a second dielectric liner adjacent respective sides of the conductive material; the second dielectric liner including an opening adjacent a portion of the conductive material; the first dielectric liner extending continuously at the portion of the conductive material; and a conductive contact extending through the first control gate, the level of dielectric material, and the opening of the second dielectric liner and contacting the conductive material of the second control gate.

First claim

What is claimed is:

1 . An apparatus comprising:
first memory cells located on a first level of the apparatus; a first control gate associated with the first memory cells and located on the first level; a level of dielectric material located on a second level of the apparatus; second memory cells located on a third level of the apparatus; a second control gate associated with the second memory cells and located on the third level, the second control gate separated from the first control gate by the level of dielectric material, the second control gate including a conductive material, a first dielectric liner adjacent a first side of the conductive material, and a second dielectric liner adjacent a second side of the conductive material, the second dielectric liner including an opening adjacent a portion of the conductive material, and the first dielectric liner extending continuously at the portion of the conductive material; a conductive contact extending through the first control gate, the level of dielectric material, and the opening of the second dielectric liner and contacting the conductive material of the second control gate.

2 . The apparatus of claim 1 , wherein the conductive material of the second control gate extends continuously at a location adjacent the opening of the second dielectric liner.

3 . The apparatus of claim 1 , wherein the first dielectric liner and the second dielectric liner include a first dielectric material, and the dielectric material located on the second level includes a second dielectric material.

4 . The apparatus of claim 1 , wherein each of the first dielectric liner and the second dielectric liner includes a dielectric material having a dielectric constant greater than a dielectric constant of silicon dioxide.

5 . The apparatus of claim 1 , wherein the conductive contact includes a conductive portion between the first dielectric liner and the first dielectric liner, and wherein the conductive portion has a footprint greater than a footprint of the opening of the second dielectric liner.

6 . The apparatus of claim 1 , wherein the conductive contact extends at least partially into the conductive material of the second control gate.

7 . The apparatus of claim 1 , wherein the conductive contact includes a conductive portion between the first dielectric liner and the second dielectric liner, wherein the conductive portion contacts the first dielectric liner.

8 . The apparatus of claim 1 , wherein the conductive contact includes a conductive pillar, and a dielectric material between the conductive pillar and the first control gate.

9 . The apparatus of claim 8 , wherein the first control gate includes an additional dielectric material adjacent the dielectric material of the conductive contact.

10 . The apparatus of claim 1 , further comprising:
third first memory cells located on a fourth level of the apparatus; a third control gate associated with the third memory cells and located on the fourth level, the second control gate including a conductive material; and an additional conductive contact extending through the second control gate and contacting the conductive material of the third control gate.

11 . An apparatus comprising:
first memory cells located on a first level of the apparatus; a first control gate associated with the first memory cells and located on the first level; a level of dielectric material located on a second level of the apparatus; second memory cells located on a third level of the apparatus; a second control gate associated with the second memory cells and located on the third level, the second control gate separated from the first control gate by the level of dielectric material, the second control gate including a conductive material, a first dielectric liner adjacent a first side of the conductive material; and a second dielectric liner adjacent a second side of the conductive material, the second dielectric liner including an opening, wherein the conductive material extends continuously at a location adjacent the opening of the second dielectric liner; and a conductive contact extending through the first control gate, the level of dielectric material, and the opening of the second dielectric liner and contacting the conductive material of the second control gate.

12 . The apparatus of claim 11 , wherein the level of dielectric material includes silicon dioxide, and each of the first dielectric liner and the second dielectric liner includes a dielectric material having a dielectric constant greater than a dielectric constant of the silicon dioxide.

13 . The apparatus of claim 11 , further comprising an additional conductive contact, wherein:
the first control gate includes an additional conductive material, a first dielectric liner adjacent a first side of the additional conductive material, and a second dielectric liner adjacent a second side of the additional conductive material, the second dielectric liner of first control gate includes including an opening; and the additional conductive contact extends through the opening of the second dielectric liner of the first control gate and contacting the additional conductive material of the first control gate.

14 . The apparatus of claim 13 , further comprising a memory cell pillar associated with one of the first memory cell and one of the second memory cells, the memory cell pillar extending through the first control gate and the second control gate, wherein:
the first control gate including a first edge; the second control gate including a second edge; the conductive contact is between the memory cell pillar and the first edge, and the first conductive contact is between the memory cell pillar and the second edge; and the additional conductive contact is between the memory cell pillar and the first edge, and the additional conductive contact between the memory cell pillar and the second edge.

15 . The apparatus of claim 14 , wherein:
the conductive contact is a first conductive contact, and the additional conductive contact is a second conductive contact; and the first conductive contact is closer to the memory cell pillar than the second conductive contact, and the first conductive contact includes a length greater than a length of the second conductive contact.

16 . The apparatus of claim 15 , further comprising third memory cells located on a fourth level of the apparatus, a third control gate associated with the third memory cells and located on the fourth level, and a third conductive contact, wherein:
the second level is between the first level and the fourth level; the third control gate includes a third conductive material, a first dielectric liner adjacent a first side of the third level of conductive material, and a second dielectric liner adjacent a second side of the third conductive material, the second dielectric liner of the third control gate including an opening; the third conductive contact extends through the opening of the second dielectric liner of the third control gate and contacting the third conductive material of the third control gate; and the third conductive contact is closer to the pillar than the first conductive contact, and the length of the first conductive contact is greater than a length of the third conductive contact.

17 . A method comprising:
forming levels of first materials interleaved with levels of second materials; forming memory cells including forming a pillar associated with the memory cells through the levels of first materials and the levels of second

Assignees

• Micron Technology Inc

Inventors

• Mazzone Giovanni
• Camerlenghi Emilio
• Gupta Sidhartha
• Tessariol Paolo
• Resnati Davide
• Carter Chet E
• List Tyler
• Paolucci Giovanni Maria

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title