Electrical interconnects for packages containing photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-2026011705-A1
Application number	US-202519328034-A
Country	US
Kind code	A1
Filing date	Sep 12, 2025
Priority date	Dec 29, 2023
Publication date	Jan 8, 2026
Grant date	—

Abstract

A semiconductor chip includes: a photonic integrated circuit (PIC) comprising an active component electrically connected to a first landing pad at a surface of the PIC, wherein the first landing pad is configured to receive a copper pillar, which, when installed, provides at least a portion of a first electrical interconnect between the active photonic component and a second integrated circuit to be stacked on the surface of the PIC, and wherein, when viewed from above the PIC towards the PIC, a center of the active photonic component on the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm.

First claim

What is claimed is:

1 . A photonic integrated circuit (PIC) comprising:
an active photonic component; a first landing pad at a first surface of the PIC, the first landing pad being configured to receive a flip-chip bump; and a first electrical interconnect electrically connecting the first landing pad to the active photonic component, wherein, when viewed from a direction perpendicular to the first surface of the PIC, a center of the active photonic component is offset from a nearest edge of the first landing pad by a distance less than 10 μm.

2 . The PIC of claim 1 , wherein the first electrical interconnect introduces a parasitic capacitance between the first landing pad and the active photonic component within a threshold level of tolerance.

3 . The PIC of claim 1 , wherein the active photonic component is an electro-absorption modulator (EAM), a ring modulator, an interference-based modulator, or a photodiode.

4 . The PIC of claim 3 , wherein the EAM comprises a diode junction, a cathode, and an anode.

5 . The PIC of claim 4 , wherein the first landing pad is electrically connected to the cathode of the EAM by the first electrical interconnect.

6 . The PIC of claim 4 , wherein the anode of the EAM is electrically connected to a bias trace routed to a second surface of the PIC that is opposite the first surface.

7 . The PIC of claim 3 , wherein the EAM is 100 μm or less in length from an input optical port to an output optical port.

8 . The PIC of claim 3 , wherein the PIC comprises a bidirectional photonic link that comprises the photodiode and a modulator,
wherein the modulator comprises at least one of: the EAM, the ring modulator, or the interference-based modulator, and wherein the bidirectional photonic link further comprises a first waveguide connecting the modulator to a unit coupled to one or more fibers, and a second waveguide connecting the photodiode to the unit coupled to the one or more fibers.

9 . The PIC of claim 1 , wherein the distance is in a range from 5 μm to 8 μm.

10 . The PIC of claim 9 , wherein the first landing pad is configured to receive the flip-chip bump having a lateral dimension of 30 μm or less.

11 . The PIC of claim 10 , wherein the first landing pad is shaped as a polygon or a circle.

12 . The PIC of claim 11 , wherein the first landing pad is larger than a lateral dimension of the flip-chip bump.

13 . The PIC of claim 11 , wherein the first landing pad has a maximum lateral dimension of 50 μm or less.

14 . The PIC of claim 1 , wherein the first surface of the PIC includes additional landing pads, the first landing pad and the additional landing pads being configured to provide electrical connections to an electronic integrated circuit (EIC) flip-chip bonded to the first surface of the PIC.

15 . The PIC of claim 14 , wherein the EIC comprises an electrical component electrically connected to the first landing pad via the flip-chip bump.

16 . The PIC of claim 15 , wherein the active photonic component is a modulator that comprises at least one of: an EAM, a ring modulator, and an interference-based modulator, and wherein the electrical component is a driver.

17 . The PIC of claim 16 , wherein, the driver and the modulator are spaced apart by about 2 mm or less.

18 . The PIC of claim 15 , wherein the PIC comprises a photodiode and the EIC further comprises a trans-impedance amplifier electrically connected to the photodiode via a second electrical interconnect comprising a second flip-chip bump between the PIC and the EIC.

19 . The PIC of claim 18 , wherein the first electrical interconnect and the second electrical interconnect each has a length of 100 μm or less.

Assignees

• Celestial Ai Inc

Inventors

• Staffaroni Matteo
• Park Kevin
• Vats Saurabh
• Sahni Subal
• Ozguc Ismail Hakki

Classifications

• G02B6/43

  Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections · CPC title

• G02F1/0157

  using electro-absorption effects, e.g. Franz-Keldysh [FK] effect or quantum confined stark effect [QCSE] · CPC title

• H10W90/732

  between stacked chips · CPC title

• G02F1/0113

  Glass-based, e.g. silica-based, optical waveguides · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title