Photonic integrated circuit package

Patent metadata

Field	Value
Publication number	US-2017194310-A1
Application number	US-201715398713-A
Country	US
Kind code	A1
Filing date	Jan 4, 2017
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

Methods, systems, and apparatus, including a photonic integrated circuit package, including a photonic integrated circuit chip, including an active optical element; an electrode configured to receive an electrical signal; a ground electrode; and a bond contact electrically coupled to the electrode; and an ASIC chip including circuitry configured to provide the electrical signal; and a bond contact that is electrically coupled to the circuitry; an bridge chip bonded to at least a portion of the photonic integrated circuit chip and at least a portion of the ASIC chip.

First claim

What is claimed is:

1 . A photonic integrated circuit package, comprising:
a photonic integrated circuit chip, comprising:
an active optical element;
an electrode configured to receive an electrical signal, wherein at least one characteristics of the active optical element is changed based on the electrical signal received by the electrode;
a ground electrode; and
a bond contact electrically coupled to the electrode; and
an ASIC (application specific integrated circuit) chip comprising:
circuitry configured to provide the electrical signal; and
a bond contact that is electrically coupled to the circuitry;
an bridge chip bonded to at least a portion of the photonic integrated circuit chip and at least a portion of the ASIC chip, the bridge chip comprising:
a conductive trace formed on a surface of the bridge chip;
a ground trace;
a first conductive contact that is directly bonded to the bond contact of the photonic integrated circuit chip; and
a second conductive contact that is directly bonded the bond contact of the ASIC chip, the first conductive contact and the second conductive contact electrically coupled to the conductive trace to provide the electrical signal from the circuitry of the ASIC chip to the electrode of the photonic integrated circuit chip.

2 . The photonic integrated circuit package of claim 1 ,
wherein the bridge chip includes a first surface in contact with the photonic integrated circuit and the ASIC chip; and a second surface opposite to the first surface, wherein the conductive trace of the bridge chip is formed on the first surface.

3 . The photonic integrated circuit package of claim 2 ,
wherein the conductive trace of the bridge chip is formed on the second surface, wherein the first conductive contact and the second conductive contact of the bridge chip is electrically coupled to the conductive trace of the bridge chip through vias formed in the bridge chip.

4 . The photonic integrated circuit package of claim 2 , wherein the conductive trace of the bridge chip is formed on a surface that is in contact with the photonic integrated circuit and the ASIC chip.

5 . The photonic integrated circuit package of claim 1 ,
wherein the photonic integrated circuit chip is a multi-element photonic integrated circuit chip that includes multiple active optical elements.

6 . The photonic integrated circuit package of claim 5 ,
wherein the multi-element photonic integrated circuit chip is a multi-channel photonic integrated circuit chip that includes a multiplexer, and wherein optical signals from multiple channels are combined by the multiplexer to provide a multiplexed optical signal.

7 . The photonic integrated circuit package of claim 5 ,
wherein the multi-element photonic integrated circuit chip is a multi-channel photonic integrated circuit chip that includes a demultiplexer, and wherein optical signals from multiple channels are demultiplexed by the demultiplexer.

8 . The photonic integrated circuit package of claim 5 ,
wherein the multi-element photonic integrated circuit chip provides optical signals without using a multiplexer or receives optical signals without using a demultiplexer.

9 . The photonic integrated circuit package of claim 5 , wherein an impedance of each conductive trace for controlling a respective active optical element of the multiple active optical elements is a controlled impedance.

10 . The photonic integrated circuit package of claim 1 ,
wherein the photonic integrated circuit chip is a single-channel photonic integrated circuit chip that includes a laser or a photodetector.

11 . The photonic integrated circuit package of claim 1 ,
wherein the photonic integrated circuit chip is an optical transceiver.

12 . The photonic integrated circuit package of claim 1 ,
wherein the photonic integrated circuit chip is fabricated on a III-V material platform or a silicon platform.

13 . The photonic integrated circuit package of claim 1 , wherein the active optical element is a lumped active optical element.

14 . The photonic integrated circuit package of claim 13 , wherein an impedance of the conductive trace of the bridge chip is a controlled impedance.

15 . The photonic integrated circuit package of claim 14 , wherein the controlled impedance is matched with an impedance of the lumped active optical element.

16 . The photonic integrated circuit package of claim 14 , wherein the controlled impedance is between 10 ohm to 200 ohm.

17 . The photonic integrated circuit package of claim 13 , wherein the conductive trace of the bridge chip comprises:
a first transmission line segment; and a second transmission line segment that is in series with the first transmission line segment, wherein dimensions of the first transmission line segment are different from dimensions of the second transmission line segment.

18 . The photonic integrated circuit package of claim 1 , wherein the active optical element is a traveling wave active optical element.

19 . The photonic integrated circuit package of claim 18 ,
wherein an arrangement of the conductive trace on the bridge chip is different from an arrangement of the multiple electrodes on the photonic integrated circuit chip, such that an arrival timing of the electrical signal at each electrode of the multiple electrodes matches with an arrival timing of an optical signal propagate in the traveling wave active optical element.

20 . The photonic integrated circuit package of claim 19 , wherein the conductive trace on the bridge chip has a serpentine pattern, and wherein the multiple electrodes on the photonic integrated circuit chip form a straight-line pattern.

21 . The photonic integrated circuit package of claim 19 , wherein a condition that the arrival timing of the electrical signal at each electrode of the multiple electrodes sufficiently matches with the arrival timing of an optical signal propagate in the traveling wave active optical element is satisfied when an inverse of a difference in the arrival timings is equal to or greater than a baud rate of the optical signal.

22 . The photonic integrated circuit package of claim 18 ,
wherein the bridge chip further comprises:
a termination resistor coupled to the conductive trace, the termination resistor having an impedance that matches with an impedance of the conductive trace.

23 . The photonic integrated circuit package of claim 22 , wherein the termination resistor is arranged to achieve a thermal isolation between the termination resistor and the active optical element of the photonic integrated circuit chip, or to provide a reduced thermal loading on the photonic integrated circuit chip or a thermoelectric cooler.

24 . The photonic integrated circuit package of claim 1 , wherein the ASIC chip is one of a lumped modulator driver (MZMD), a traveling wave MZMD, or a transimpedance amplifier (TIA).

25 . The photonic integrated circuit package of claim 1 ,
wherein a first pitch between elements in the photonic integrated circuit chip is different from a second pitch between elements in the ASIC chip, and wherein the bridge chip provides a fan out of conductive traces that expand from the first pitch to the second pitch.

26 . The photonic integrated circuit package of claim 1 ,
wherein the bridge chip includes an optical access configured couple light to or from the photon

Assignees

• Infinera Corp

Inventors

• Evans Peter W
• Osenbach John W
• Kish Jr Fred A
• Zhang Jiaming
• Olmedo Miguel Iglesias
• Anagnosti Maria

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title