Image sensor

Patent metadata

Field	Value
Publication number	US-2026006933-A1
Application number	US-202418988162-A
Country	US
Kind code	A1
Filing date	Dec 19, 2024
Priority date	Jun 27, 2024
Publication date	Jan 1, 2026
Grant date	—

Abstract

An image sensor may include a substrate and a plurality of pixel regions. At least one of the plurality of pixel regions includes a photoelectric conversion portion in the substrate and a pixel circuit adjacent to the first surface of the substrate. The pixel circuit may include a plurality of buried patterns, which each may have a buried structure in the substrate. The pixel circuit may include a first transistor including a first gate electrode and a second transistor including a second gate electrode. The first gate electrode may be a vertical transfer gate electrode. A cross-sectional shape of the second gate electrode may be different from a cross-sectional shape of the first gate electrode. The plurality of buried patterns may include the first gate electrode and the second gate electrode.

First claim

What is claimed is:

1 . An image sensor, comprising:
a substrate including a first surface and a second surface opposite each other; and a plurality of pixel regions, at least one of the plurality of pixel regions including a photoelectric conversion portion in the substrate and a pixel circuit adjacent to the first surface of the substrate, wherein the pixel circuit includes a plurality of buried patterns, each of the plurality of buried patterns having a buried structure in the substrate, wherein the pixel circuit includes a first transistor and a second transistor, wherein the first transistor includes a first gate electrode and the second transistor includes a second gate electrode, wherein the first gate electrode is a vertical transfer gate electrode and a cross-sectional shape of the second gate electrode is different from a cross-sectional shape of the first gate electrode, and wherein the plurality of buried patterns include the first gate electrode and the second gate electrode.

2 . The image sensor of claim 1 , wherein the plurality of buried patterns include a same base material.

3 . The image sensor of claim 1 , wherein
the plurality of buried patterns each include a surface, in each of the plurality of buried patterns, the surface includes a concave portion having a concave shape and including a portion between the first surface of the substrate and the second surface of the substrate, or the plurality of surfaces of the plurality of buried patterns have a same surface property, or a corner portion of each of the plurality of buried patterns includes a rounded portion.

4 . The image sensor of claim 1 , wherein
an inner portion of the second gate electrode is between both of side portions of the second gate electrode, and the second gate electrode includes a depth change portion where a depth of the inner portion of the second gate electrode is different than a depth of both of the side portions of the second gate electrode.

5 . The image sensor of claim 1 , further comprising:
device isolation portions at both sides of the second gate electrode.

6 . The image sensor of claim 1 , wherein
the pixel circuit includes a plurality of second transistors and the second transistor is one of the plurality of second transistors, the plurality of second transistors are configured to perform different operations in the plurality of pixel regions, and the plurality of second transistors respectively including a plurality of second gate electrodes having same cross-sectional structures.

7 . The image sensor of claim 1 , wherein
the pixel circuit includes a source follower transistor and at least one of a reset transistor or a selection transistor, a thickness of a gate insulation layer of the first transistor or a thickness of a gate insulation layer of the second transistor is greater than a thickness of a gate insulation layer of the source follower transistor, and the second transistor is the reset transistor or the selection transistor.

8 . The image sensor of claim 1 , wherein
the plurality of buried patterns include at least one of a doping connection pattern or a wiring pattern, the doping connection pattern has a buried structure in the substrate and is connected to the substrate or a doping region in the substrate, and the wiring pattern has a buried structure in the substrate.

9 . The image sensor of claim 1 , wherein
the substrate includes a doping region, the doping region includes at least one of a floating diffusion region or a ground region in a portion of the substrate adjacent to the first surface of the substrate, the plurality of buried patterns include at least one of a first connection pattern connected to the ground region or a second connection pattern connected to the floating diffusion region.

10 . The image sensor of claim 9 , further comprising
an isolation portion disposed to correspond to a boundary of the plurality of pixel regions, wherein the first connection pattern or the second connection pattern is in at least two pixel regions of the plurality of pixel regions, and at least a partial portion of the first connection pattern or the second connection pattern is on the isolation portion.

11 . The image sensor of claim 9 , further comprising
a wiring portion that is disposed on the first surface of the substrate and includes a first contact via electrically connected to the pixel circuit; and an isolation portion disposed to correspond to a boundary of the plurality of pixel regions, wherein at least a partial portion of the first contact via is connected to the first connection pattern or the second connection pattern in a portion overlapping the isolation portion in a plan view.

12 . The image sensor of claim 9 , wherein
the plurality of pixel regions include a first pixel region, a second pixel region, a third pixel region, and a fourth pixel region, the first pixel region and the second pixel region are adjacent to each other in a first direction, the third pixel region and the fourth pixel region that are adjacent to the first pixel region and the second pixel region, respectively, in a second direction, the second direction crosses the first direction, the first connection pattern is in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region and the first connection pattern is connected to ground regions in the first pixel region, the second pixel region, the third pixel region, and the fourth pixel region, respectively, the second connection pattern includes a first connection portion and a second connection portion, the first connection portion of the second connection pattern is in the first pixel region and the third pixel region and is connected to floating diffusion regions in the first pixel region and the third pixel region, respectively, the second connection portion of the second connection pattern is in the second pixel region and the fourth pixel region and is connected to floating diffusion regions in the second pixel region and the fourth pixel region, respectively.

13 . The image sensor of claim 1 , wherein
the plurality of buried patterns include a connection pattern and a wiring pattern, wherein the connection pattern has a buried structure in the substrate and is connected to a floating diffusion region adjacent to the first surface of the substrate, and wherein the wiring pattern connects the second gate electrode of the second transistor to the connection pattern.

14 . An image sensor, comprising:
a substrate including a first surface and a second surface opposite each other; and a plurality of pixel regions, at least one of the plurality of pixel regions including a photoelectric conversion portion in the substrate and a pixel circuit adjacent to the first surface of the substrate; wherein the pixel circuit includes a plurality of buried patterns, each of the plurality of buried patterns having a buried structure in the substrate, wherein the pixel circuit includes a first transistor, a second transistor, and a connection pattern, wherein the first transistor includes a first gate electrode and the second transistor includes a second gate electrode, wherein a cross-sectional shape of the second gate electrode is different from a cross-sectional shape of the first gate electrode, wherein the connection pattern includes at least one of a doping connection pattern or a wiring pattern, and wherein the plurality of buried patterns include the second gate electrode and the connection pattern.

15 . The image sen

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Mintae
• Kim Donghyun
• Lee Dong-Chul
• Lee Tae-Hun
• Choi Sungsoo

Classifications

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/811 Primary

  Interconnections · CPC title

• H10F39/813

  Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/8037 Primary

  the integrated elements comprising a transistor · CPC title