Semiconductor device including active pattern

Patent metadata

Field	Value
Publication number	US-2025393201-A1
Application number	US-202519058005-A
Country	US
Kind code	A1
Filing date	Feb 20, 2025
Priority date	Jun 24, 2024
Publication date	Dec 25, 2025
Grant date	—

Abstract

A semiconductor device includes a bit line structure, a back gate structure extending on the bit line structure in a first horizontal direction, the back gate structure including a back gate electrode and an upper capping layer on the back gate electrode, a word line structure disposed on the bit line structure, the word line structure including a word line and a gate dielectric layer covering a side surface of the word line, an active pattern disposed on the bit line structure, the active pattern extending in a vertical direction between the back gate structure and the word line structure, and a contact pattern on the active pattern. The upper capping layer includes a seam extending in the first horizontal direction.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a bit line structure; a back gate structure extending on the bit line structure in a first horizontal direction, the back gate structure including a back gate electrode and an upper capping layer on the back gate electrode; a word line structure disposed on the bit line structure, the word line structure including a word line and a gate dielectric layer covering a side surface of the word line; an active pattern disposed on the bit line structure, the active pattern extending in a vertical direction between the back gate structure and the word line structure; and a contact pattern on the active pattern, wherein the upper capping layer includes a seam extending in the first horizontal direction.

2 . The semiconductor device of claim 1 , wherein, in a plan view:
the active pattern includes a first edge portion adjacent to the back gate structure, and a second edge portion adjacent to the word line structure, and at least one of the first edge portion and the second edge portion is rounded.

3 . The semiconductor device of claim 2 , wherein both the first edge portion and the second edge portion are rounded.

4 . The semiconductor device of claim 3 , wherein a radius of curvature of the first edge portion is different from a radius of curvature of the second edge portion.

5 . The semiconductor device of claim 1 , wherein the back gate structure further includes a back gate dielectric layer in contact with a portion of the gate dielectric layer of the word line structure, and
wherein, in a plan view: the active pattern has a first side surface adjacent to the back gate structure, a second side surface opposite to the first side surface, and a third side surface and a fourth side surface spaced apart from each other in the first horizontal direction, the first side surface is in contact with the back gate dielectric layer of the back gate structure, and the second side surface, the third side surface, and the fourth side surface are in contact with the gate dielectric layer of the word line structure.

6 . The semiconductor device of claim 5 , wherein at least a portion of the third side surface and at least a portion of the fourth side surface overlap the word line in the first horizontal direction.

7 . The semiconductor device of claim 5 , wherein the active pattern has curved surfaces in at least one of first portions between the first side surface and the third side surface and between the first side surface and the fourth side surface, and second portions between the second side surface and the third side surface and between the second side surface and the fourth side surface.

8 . The semiconductor device of claim 1 , wherein, in a plan view:
the active pattern includes a first side surface adjacent to the back gate structure, a second side surface opposite to the first side surface, and a third side surface and a fourth side surface spaced apart from each other in the first horizontal direction, the first side surface has a first width in the first horizontal direction, and the first width is less than a maximum width of the active pattern in the first horizontal direction.

9 . The semiconductor device of claim 8 , wherein at least one of the third and fourth side surfaces has a second width in a second horizontal direction, intersecting the first horizontal direction, and
wherein the second width is less than a maximum width of the active pattern in the second horizontal direction.

10 . The semiconductor device of claim 1 , further comprising:
a liner overlapping the active pattern in the first horizontal direction, wherein the back gate structure further includes a back gate dielectric layer disposed between the back gate electrode and the active pattern, the back gate dielectric layer extending in the first horizontal direction, and wherein the liner is in contact with the active pattern and the back gate dielectric layer.

11 . The semiconductor device of claim 10 , wherein the liner extends in the first horizontal direction between the back gate dielectric layer and the gate dielectric layer.

12 . The semiconductor device of claim 10 , wherein, in a plan view, a side surface of the liner has a curved surface.

13 . The semiconductor device of claim 10 , wherein a density of the liner is lower than a density of the back gate dielectric layer.

14 . The semiconductor device of claim 10 , wherein a maximum horizontal width of the liner in a second horizontal direction, intersecting the first horizontal direction, is less than a horizontal width of the active pattern in the second horizontal direction.

15 . The semiconductor device of claim 10 , wherein a side surface of the active pattern extending in a second horizontal direction, intersecting the first horizontal direction, is in contact with the liner and the gate dielectric layer.

16 . A semiconductor device comprising:
a bit line structure on a cell array region; a back gate structure extending from the cell array region to an interface region, on the bit line structure, the back gate structure including a back gate electrode and an upper capping layer on the back gate electrode; a word line structure disposed on the bit line structure, the word line structure extending from the cell array region to the interface region, the word line structure including a word line and a gate dielectric layer covering a side surface of the word line; an active pattern disposed on the bit line structure, on the cell array region, the active pattern extending in a vertical direction between the back gate structure and the word line structure; and a contact pattern on the active pattern, wherein the upper capping layer includes a seam extending from the cell array region to the interface region.

17 . The semiconductor device of claim 16 , wherein the back gate electrode continuously extends from the cell array region to the interface region.

18 . The semiconductor device of claim 17 , wherein an upper surface of the back gate electrode in the cell array region is disposed on a level, the same as that of an upper surface of the back gate electrode in the interface region.

19 . The semiconductor device of claim 16 , wherein the word line continuously extends from the cell array region to the interface region.

20 . A semiconductor device comprising:
a bit line structure; a back gate structure extending on the bit line structure in a first horizontal direction, the back gate structure including a back gate electrode and an upper capping layer on the back gate electrode; a word line structure disposed on the bit line structure, the word line structure including a word line and a gate dielectric layer covering a side surface of the word line; an active pattern disposed on the bit line structure, the active pattern extending in a vertical direction between the back gate structure and the word line structure; a contact pattern on the active pattern; and an information storage structure on the contact pattern, wherein, in a plan view: at least two side surfaces of the active pattern are in contact with the gate dielectric layer, the upper capping layer includes a seam extending in the first horizontal direction, and a lower end and an upper end of the seam are disposed between a lower surface and an upper surface of the upper capping layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyunjin
• Park Jiho
• Kim Yongkwan
• Kim Huijung
• Chae Heejae

Classifications

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/488 Primary

  Word lines · CPC title

• H10B12/482 Primary

  Bit lines · CPC title