Semiconductor structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-2025391663-A1
Application number	US-202418941682-A
Country	US
Kind code	A1
Filing date	Nov 8, 2024
Priority date	Jun 21, 2024
Publication date	Dec 25, 2025
Grant date	—

Abstract

A method includes forming a first fin protruding from a substrate at a center region, and a second fin protruding from the substrate at an edge region, the first fin and second fin each including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack. A patterning material is deposited adjacent to and over each of the first fin and the second fin. Different etch process parameters are used to etch the first fin at the center region than the etch process parameters of the second fin at the edge region.

First claim

What is claimed is:

1 . A method, comprising:
providing a substrate having a first region at a center zone and a second region at an edge zone; forming a first fin protruding from the substrate at the first region and a second fin protruding from the substrate at the second region, the first fin and the second fin each including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including alternating first and second semiconductor layers of different material compositions and wherein the hard mask layer includes an oxide layer and a nitride layer over the oxide layer; performing a first etching process to remove the nitride layer from the first fin in the first region using a first process temperature and to remove the nitride layer from the second fin in the second region using a second process temperature, wherein the second process temperature is lower than the first process temperature; performing a second etching process to remove the oxide layer from the first fin in the first region proving an increased plasma concentration at the second region than the first region during the second etching process; and performing additional etching to remove a portion of the first fin and a portion of the second fin.

2 . The method of claim 1 , wherein the first etching process etches the nitride layer and stops at an upper surface of the oxide layer.

3 . The method of claim 1 , wherein there the second etching process etching the oxide layer and exposing an upper surface of the epitaxial stack.

4 . The method of claim 1 , further comprising:
depositing a patterning material over the first fin and the second fin, wherein the patterning material includes a bottom layer over and adjacent the first fin and the second fin.

5 . The method of claim 4 , wherein the first etching process and the second etching process etch the bottom layer adjacent the first fin and the second fin.

6 . The method of claim 1 , wherein the increased plasma concentration is provided by providing a transformer-coupled capacitive tuning (TCCT) parameter less than one.

7 . The method of claim 1 , wherein the increased plasma concentration is provided by providing a bias voltage at the first region less than a bias voltage at the second region.

8 . The method of claim 1 , wherein the performing additional etching to remove the portion of the first fin and the portion of the second fin forms a first recess in the first fin and a second recess in the second fin.

9 . The method of claim 8 , further comprising: depositing dielectric material in the first recess and the second recess.

10 . The method of claim 9 , wherein each of the first recess and the second recess include a bulb-shape within the fin base.

11 . A method, comprising:
providing a substrate having a center zone and an edge zone; forming a first fin protruding from the substrate in the center zone and a second fin protruding from the substrate in the edge zone, the first fin and second fin each including a dielectric portion over a semiconductor portion; forming a bottom patterning layer adjacent the first fin and the second fin and over the dielectric portion of the first fin and the second fin; and performing a plasma etching process to etch the bottom patterning layer adjacent the first fin and the dielectric portion of the first fin with a first set of process parameters while concurrently etching the bottom resist layer adjacent the second fin and the dielectric portion of the second fin with a second set of process parameters different than the first set of process parameters.

12 . The method of claim 11 , wherein the performing the plasma etching process includes:
performing a first step to remove a nitride layer of the dielectric portion of the first fin and a nitride layer of the dielectric portion of the second fin; and performing a second step to remove an oxide layer of the dielectric portion of the first fin and an oxide layer of the dielectric portion of the second fin.

13 . The method of claim 12 , wherein after performing the second step a top surface of the semiconductor portion of the first fin and a top surface of the semiconductor portion of the second fin are exposed.

14 . The method of claim 12 , wherein the first step includes a first temperature in the first set of process parameters and a second temperature in the second set of process parameters, wherein the first temperature is greater than the second temperature.

15 . The method of claim 14 , wherein the second step includes a transformer-coupled capacitive tuning (TCCT) of 0 . 3 .

16 . The method of claim 11 , wherein the first set of process parameters includes a first temperature and the second set of process parameters includes a second temperature, the second temperature lower than the first temperature.

17 . The method of claim 11 , wherein the performing the plasma etching is performed at a transformer-coupled capacitive tuning (TCCT) providing a first bias voltage at the center zone and a second bias voltage at the edge zone.

18 . A semiconductor device, comprising:
a first fin base protruding from a center region of a substrate and a second fin base protruding from an edge region of the substrate; a first plurality of nanostructures above the first fin base; a second plurality of nanostructures above the second fin base; and a first isolation feature disposed on an edge of the first fin base and a second isolation feature disposed on an edge of the second fin base, wherein the edge of the first fin base is substantially similar in profile of the edge of the second fin base.

19 . The semiconductor device of claim 18 , wherein the edge region of the substrate includes approximately 10% of the substrate adjacent an edge of the substrate.

20 . The semiconductor device of claim 18 , wherein a profile of the edge of the first fin base is curvilinear and a profile of the edge of the second fin base is curvilinear.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Shin-Li
• Lin Kai Ju
• Liu zu-yin
• Wu Chi-Chen
• Lee Szu-Ping
• Lin You-Ting
• Kuo Jiun-Ming
• Peng Yuan-Ching
• Chen Chen-Ping

Classifications

• H10D62/364

  of IGFETs · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title