Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025391441-A1
Application number	US-202519035485-A
Country	US
Kind code	A1
Filing date	Jan 23, 2025
Priority date	Jun 24, 2024
Publication date	Dec 25, 2025
Grant date	—

Abstract

A semiconductor memory device includes a plurality of conductive layers arranged in a vertical direction, a plurality of active layers connected to the plurality of conductive layers, a plurality of pass gates each penetrating the plurality of active layers, and a plurality pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a plurality of cell pillar structures extending in a vertical direction, the plurality of cell pillar structures being arranged to be spaced apart from each other in a horizontal direction; a word line stack structure surrounding the plurality of cell pillar structures, the word line stack structure including a plurality of cell gate layers arranged to be spaced apart from each other in the vertical direction; a plurality of cell level contact conductive layers spaced apart from the plurality of cell gate layers in the horizontal direction, the plurality of cell level contact conductive layers being arranged to be spaced apart from each other in the vertical direction; a plurality of cell level active layers connected to the plurality of cell gate layers, the plurality of cell level active layers extending in the horizontal direction to be connected to the plurality of cell level contact conductive layers, the plurality of cell level active layers being arranged to be spaced apart from each other in the vertical direction; a plurality of pass gates spaced apart from each other in the horizontal direction, each of the plurality of pass gates penetrating the plurality of cell level active layers; a plurality of pass gate insulating layers surrounding sidewalls of the plurality of pass gates, respectively; and a plurality of insulative pillar structures alternately disposed one by one in the horizontal direction with the plurality of pass gates, the plurality of insulative pillar structures penetrating the plurality of cell level active layers.

2 . The semiconductor memory device of claim 1 , further comprising a plurality of conductive gate contact structures corresponding to a plurality of rows configured with the plurality of pass gates,
wherein two or more of the plurality of pass gates on each of the plurality of rows are arranged in a line in a first direction, and wherein each of the plurality of conductive gate contact structures extends in the first direction to be connected to pass gates of a corresponding row among the plurality of rows.

3 . The semiconductor memory device of claim 2 , further comprising:
a conductive connection pattern connected to the plurality of conductive gate contact structures; and a block select line connected to the plurality of pass gates via the plurality of conductive gate contact structures, and the conductive connection pattern.

4 . The semiconductor memory device of claim 1 , wherein the plurality of cell level active layers and the plurality of pass gates form a pass transistor group connected to the plurality of cell gate layers.

5 . The semiconductor memory device of claim 1 , further comprising a plurality of global conductive patterns connected to the plurality of cell level contact conductive layers, the plurality of global conductive patterns extending in the vertical direction.

6 . The semiconductor memory device of claim 1 , further comprising a source select gate layer and a drain select gate layer, spaced apart from each other in the vertical direction with the word line stack structure interposed therebetween, the source select gate layer and the drain select gate layer, surrounding the plurality of cell pillar structures.

7 . The semiconductor memory device of claim 6 , further comprising a select isolation structure penetrating the drain select gate layer, the select isolation structure isolating the drain select gate layer into at least two drain select lines surrounding different cell pillar structures among the plurality of cell pillar structures.

8 . The semiconductor memory device of claim 7 , further comprising:
a drain select level active layer extending in the horizontal direction from each of the at least two drain select lines, the drain select level active layer surrounding a corresponding pass gate among the plurality of pass gates; and a drain select level contact conductive layer extending in the horizontal direction from the drain select level active layer, wherein the select isolation structure extends to penetrate the drain select level active layer and the drain select level contact conductive layer.

9 . The semiconductor memory device of claim 8 , wherein the drain select level active layer and the corresponding pass gate form a pass transistor connected to a corresponding drain select line among the at least two drain select lines.

10 . The semiconductor memory device of claim 8 , further comprising a global conductive pattern connected to the drain select level contact conductive layer, the global conductive pattern extending in the vertical direction.

11 . The semiconductor memory device of claim 7 , further comprising at least two conductive local contact structures respectively extending in the vertical direction from the at least two drain select lines.

12 . The semiconductor memory device of claim 11 , further comprising:
a plurality of global conductive patterns respectively connected to the plurality of cell level contact conductive layers, the plurality of global conductive patterns extending in the vertical direction; and a plurality of conductive gate contact structures corresponding to a plurality of rows configured with the plurality of pass gates, the plurality of conductive gate contact structures extending in a first direction to be connected to pass gates of a corresponding row among the plurality of rows, wherein the plurality of conductive gate contact structures are disposed between the at least two conductive local contact structures and the plurality of global conductive patterns.

13 . The semiconductor memory device of claim 6 , further comprising:
a source select level active layer extending in the horizontal direction from the source select gate layer, the source select level active layer surrounding the plurality of pass gates; and a source select level contact conductive layer extending in the horizontal direction from the source select level active layer.

14 . The semiconductor memory device of claim 13 , wherein the source select level active layer and the plurality of pass gates form a pass transistor group connected to the source select gate layer.

15 . The semiconductor memory device of claim 13 , further comprising a global conductive pattern connected to the source select level contact conductive layer, the global conductive pattern extending in the vertical direction.

16 . A semiconductor memory device comprising:
a source layer having a first surface and a second surface, which face in directions opposite to each other and extend in a horizontal direction; a bit line disposed to be spaced apart from the second surface of the source layer in a vertical direction; a plurality of insulating layers including a local region, a global region spaced apart from the local region in the horizontal direction, and a pass transistor array region between the local region and the global region, the plurality of insulating layers being spaced apart from each other in the vertical direction between the second surface of the source layer and the bit line; a plurality of first conductive layers alternately disposed one by one in the vertical direction with the plurality of insulating layers in the local region; a plurality of cell pillar structures penetrating the plurality of first conductive layers and the plurality of insulating layers; a plurality of active layers alternately disposed one by one in the vertical direction with the plurality of insulating layers in the pass transistor

Assignees

• Sk Hynix Inc

Inventors

• Choi Seok Min
• Jang Jung Shik
• Kwak Rho Gyu
• Park Mi Seong
• Park In Su
• Yang Na Yeong
• Choi Won Geun

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title