Coaxial vias in glass core architectures

Patent metadata

Field	Value
Publication number	US-2025386432-A1
Application number	US-202418745634-A
Country	US
Kind code	A1
Filing date	Jun 17, 2024
Priority date	Jun 17, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

In one embodiment, a substrate includes a glass core layer with a plurality of coaxial through glass vias (TGVs). The coaxial TGVs include a first conductive portion and a second conductive portion with a dielectric therebetween. An outer conductive portion of the coaxial TGV may be formed using electroplated metal while an inner conductive portion of the TGV may be formed using metal sintering paste.

First claim

1 . An apparatus comprising:
a glass layer defining an opening between a first side of the glass layer and a second side of the glass layer opposite the first side; a first conductive layer inside the opening, the first conductive layer electrically coupling the first side of the glass layer and the second side of the glass layer; a second conductive layer inside the first conductive layer, the second conductive layer electrically coupling the first side of the glass layer and the second side of the glass layer; and a dielectric between the first conductive layer and the second conductive layer.

2 . The apparatus of claim 1 , wherein the second conductive layer comprises a sintered metal.

3 . The apparatus of claim 2 , wherein the second conductive layer further comprises a filler material.

4 . The apparatus of claim 3 , wherein the filler material comprises one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

5 . The apparatus of claim 1 , wherein the dielectric comprises an organic material.

6 . The apparatus of claim 5 , wherein the organic material comprises one or more of polyimide, polybenzoaxazole, polycarbonate, benzocyclobutene (BCB), poly(vinyl pyridine) (PVP), polyphenol, polyether, and polyacrylate.

7 . The apparatus of claim 1 , wherein the first conductive layer has a generally annular cross section, and the second conductive layer has a generally circular cross section.

8 . The apparatus of claim 1 , wherein the dielectric is a first dielectric, and the apparatus further comprises a second dielectric between the glass layer and the first conductive layer.

9 . The apparatus of claim 8 , wherein the second dielectric comprises a polymer.

10 . The apparatus of claim 8 , wherein the second dielectric comprises silicon and one of oxygen and nitrogen.

11 . The apparatus of claim 1 , further comprising buildup layers above the glass layer, wherein a first metal trace in the buildup layers is connected to the first conductive layer and a second metal trace in the buildup layers is connected to the second conductive layer.

12 . A device comprising the apparatus of claim 1 and an integrated circuit die coupled to the apparatus.

13 . An apparatus comprising:
a glass core layer comprising a plurality of through glass vias (TGVs), at least one TGV comprising:
an inner conductive layer extending from a top surface of the glass core layer to a bottom surface of the glass core layer;
an outer conductive layer extending from the top surface to the bottom surface; and
a dielectric between the inner conductive layer and the outer conductive layer and extending from the top surface to the bottom surface; and
buildup layers on the glass core layer comprising metal traces, wherein a first metal trace of the buildup layers is connected to the inner conductive layer and a second metal trace of the buildup layers is connected to the outer conductive layer.

14 . The apparatus of claim 13 , wherein the inner conductive layer comprises a sintered metal.

15 . The apparatus of claim 14 , wherein the inner conductive layer further comprises one of diamond, boron nitride, aluminum oxide, magnesium oxide, and silicon oxide.

16 . The apparatus of claim 13 , wherein the dielectric comprises an organic material.

17 . A device comprising the apparatus of claim 13 and an integrated circuit die coupled to the apparatus.

18 . A system comprising:
an integrated circuit die; and a package substrate comprising circuitry to interconnect the integrated circuit die with a circuit board, the package substrate comprising:
a glass core layer;
a plurality of coaxial through-glass vias (TGVs) in the glass core layer, the coaxial TGVs extending from a top surface of the glass core layer to the bottom surface of the glass core layer and comprising:
an outer conductive layer;
an inner conductive layer; and
a dielectric between the inner conductive layer and the outer conductive layer.

19 . The system of claim 18 , further comprising a dielectric between the outer conductive layer and the glass core layer.

20 . The system of claim 18 , further comprising a circuit board coupled to the package substrate, wherein the integrated circuit die comprises a processor.

Assignees

• Intel Corp

Inventors

• Carrazzone Ryan Joseph
• Arrington Kyle J
• Shan Bohan
• Xu Dingying
• Pietambaram Srinivas Venkata Ramanuja

Classifications

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H05K2201/0979

  Redundant conductors or connections, i.e. more than one current path between two points · CPC title

• H05K2201/09827

  Tapered, e.g. tapered hole, via or groove · CPC title

• H05K3/426

  initial plating of through-holes in substrates without metal · CPC title

• H10W70/635

  Through-vias · CPC title