Compensation of analog-to-digital converter (adc) gain error

Patent metadata

Field	Value
Publication number	US-2025385681-A1
Application number	US-202519242679-A
Country	US
Kind code	A1
Filing date	Jun 18, 2025
Priority date	Jun 18, 2024
Publication date	Dec 18, 2025
Grant date	—

Abstract

A method may include generating, via a sigma-delta DAC, a series of analog voltage levels that are equally spaced across a selected portion of ADC range; measuring, via the ADC, the series of analog voltages levels generated via the sigma-delta DAC; determining an error of a system at least partially based on a comparison of ADC output values and expected ADC output values, the system including the sigma-delta DAC and the ADC; modeling the error of the system using a combination of piecewise linear basis functions representing different types of errors or offsets; and determining a gain error of the ADC at least partially based on a coefficient of a linear basis function corresponding to the gain error of the ADC, the linear basis function one of the piecewise linear basis functions used to model the error of the system.

First claim

What is claimed is:

1 . An apparatus, comprising:
an analog-to-digital converter (ADC); a sigma-delta digital-to-analog-converter (DAC); and a gain-error compensation logic to:
control the sigma-delta DAC to generate DC output voltages within a selected portion of the operating range of the ADC;
determine an error of the system at least partially based on a comparison of expected ADC output values and ADC output values generated by the ADC in response to the generated DC output voltages;
model the error of the system using a combination of piecewise linear basis functions representing different types of errors or offsets; and
determine a gain error of the ADC at least partially based on a coefficient of a linear basis function corresponding to the gain error of the ADC, the linear basis function one of the piecewise linear basis functions used to model the error of the system.

2 . The apparatus of claim 1 , wherein to control the sigma-delta DAC to generate DC output voltages within the selected portion of the operating range of the ADC, the gain-error compensation logic to:
command the DAC to generate substantially DC output-voltage levels uniformly spaced across a selected portion of an input-voltage range of the ADC.

3 . The apparatus of claim 2 , wherein the gain-error compensation logic to:
determine, for respective output-voltage levels, a difference between an expected ADC code value and an ADC code value produced by the ADC in response to a respective output-voltage level; and use the determined difference in the comparison of expected ADC output values and ADC output values generated by the ADC in response to the generated DC output voltages.

4 . The apparatus of claim 1 , wherein the combination of piecewise linear basis functions representing different types of errors or offsets includes piecewise linear basis functions respectively representing offset error, gain error, or a higher-order error component that captures non-ideal behavior.

5 . The apparatus of claim 4 , wherein the higher-order error component that captures non-ideal behavior is:
a triangle error component represented by a unit-triangle basis function, the triangle error attributable to timing mismatch between high-side and low-side drive transistors of the sigma-delta DAC, or a differential-offset error component represented by a half-sign basis function, the differential-offset error attributable to offset-voltage mismatch between P-channel and N-channel input stages of a buffer stage of the sigma-delta DAC.

6 . The apparatus of claim 1 , wherein the gain-error-compensation logic to accumulate system-error values into first-order scalars S 1L and S 1R and second-order scalars S 2L and S 2R , each scalar corresponding to a respective lower-range or upper-range half of the selected portion of the ADC input-voltage range.

7 . The apparatus of claim 6 , wherein the gain-error-compensation logic to determine the coefficient of the linear basis function by solving a least-squares normal equation expressed exclusively in terms of the scalars S 1L , S 1R , S 2L , and S 2R .

8 . The apparatus of claim 1 , comprising a calibration register to store the determined gain-error value, and wherein the gain-error-compensation logic to apply a gain-compensation factor derived from the calibration register to subsequent ADC output values generated during normal operation.

9 . The apparatus of claim 1 , wherein the selected portion of the input-voltage range spans approximately one-half of a full-scale input range of the ADC.

10 . The apparatus of claim 1 , wherein the sigma-delta DAC and the ADC are monolithically integrated on a common semiconductor die.

11 . A method comprising:
generating, via a sigma-delta DAC, a series of analog voltage levels that are equally spaced across a selected portion of ADC range; measuring, via the ADC, the series of analog voltages levels generated via the sigma-delta DAC; determining an error of a system at least partially based on a comparison of ADC output values and expected ADC output values, the system including the sigma-delta DAC and the ADC; modeling the error of the system using a combination of piecewise linear basis functions representing different types of errors or offsets; and determining a gain error of the ADC at least partially based on a coefficient of a linear basis function corresponding to the gain error of the ADC, the linear basis function one of the piecewise linear basis functions used to model the error of the system.

12 . The method of claim 11 , wherein generating the series of analog-voltage levels comprises:
commanding the sigma-delta DAC to output substantially DC voltage levels that are uniformly spaced across the selected portion of the ADC input-voltage range.

13 . The method of claim 12 , comprising:
determining, for each generated analog-voltage level, a difference between (i) an expected ADC code value for the respective analog-voltage level and (ii) an ADC code value produced by the ADC in response to the respective analog-voltage level, and using the determined differences in the comparison of expected and measured ADC output values.

14 . The method of claim 11 , wherein the combination of piece-wise-linear basis functions includes basis functions respectively representing offset error, gain error, and at least one higher-order error component.

15 . The method of claim 14 , wherein the higher-order error component comprises:
a triangle-error component represented by a unit-triangle basis function, the triangle error attributable to timing mismatch between high-side and low-side drive transistors of the sigma-delta DAC; or a differential-offset error component represented by a half-sign basis function, the differential-offset error attributable to offset-voltage mismatch between P-channel and N-channel input stages of a buffer stage of the sigma-delta DAC.

16 . The method of claim 11 , comprising:
accumulating the system-error values into first-order scalars S 1 L and S 1 R and second-order scalars S 2 L and S 2 R, each scalar corresponding to a respective lower-range or upper-range half of the selected portion of the ADC input-voltage range.

17 . The method of claim 16 , comprising:
solving a least-squares normal equation that is expressed exclusively in terms of the scalars S 1 L, S 1 R, S 2 L, and S 2 R to obtain the coefficient of the linear basis function corresponding to the gain error of the ADC.

18 . The method of claim 11 , comprising:
storing the determined gain-error value in a calibration register; and applying, during subsequent normal operation, a gain-compensation factor derived from the calibration register to ADC output values generated in response to input signals.

19 . The method of claim 11 ,
wherein the selected portion of the ADC input-voltage range spans approximately one-half of a full-scale input range of the ADC.

20 . The method of claim 11 ,
wherein the sigma-delta DAC and the ADC are monolithically integrated on a common semiconductor die.

21 . A system or apparatus, comprising:
at least one processor; and a memory to store instructions that, upon execution by the at least one processor, to enable the processor to: command a sigma-delta digital-to-analog converter (DAC) to generate multiple substantially-DC analog-voltage levels that are uniformly spaced across a selected portion of an input-voltage range of an analog-to-digital converter (ADC) coup

Assignees

• Microchip Tech Inc

Inventors

• Sachs Jason M
• Stewart William Henry

Classifications

• H03M3/354

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03M3/504

  the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC · CPC title

• H03M1/1038

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title