Protective moisture barrier and crack stop structure for ic chip using air gap in liner in deep trench

Patent metadata

Field	Value
Publication number	US-2025372535-A1
Application number	US-202418731564-A
Country	US
Kind code	A1
Filing date	Jun 3, 2024
Priority date	Jun 3, 2024
Publication date	Dec 4, 2025
Grant date	—

Abstract

A structure includes an integrated circuit (IC) chip including an IC region and a peripheral region around the IC region. A first continuous deep trench (DT) is defined in the peripheral region around the IC region, and an air gap is defined by a first dielectric liner in the first continuous DT. The structure provides a moisture barrier and a crack stop.

First claim

What is claimed is:

1 . A structure, comprising:
an integrated circuit (IC) chip including an IC region and a peripheral region around the IC region; a first continuous deep trench (DT) defined in the peripheral region around the IC region; and an air gap defined by a first dielectric liner in the first continuous DT.

2 . The structure of claim 1 , further comprising:
a second continuous deep trench (DT) defined in a scribe region of the peripheral region around the first continuous DT; and a second dielectric liner in the second continuous DT, wherein the second continuous DT has an open upper end.

3 . The structure of claim 2 , further comprising a segmented metal seal ring between the first continuous DT and the second continuous DT.

4 . The structure of claim 2 , wherein the first continuous DT has a maximum width, excluding the first dielectric liner, in a range of 1.0 to 1.5 micrometers, and the second continuous DT has a maximum width, excluding the second dielectric liner, in a range of 6 to 30 micrometers.

5 . The structure of claim 2 , wherein the first continuous DT includes a plurality of first continuous DTs that are concentrically arranged.

6 . The structure of claim 1 , wherein the first dielectric liner includes a silicon nitride layer over a silicon oxide layer.

7 . The structure of claim 1 , wherein the first dielectric liner is contiguous with a passivation layer over the IC chip, and the air gap has an upper end at least covered by the passivation layer.

8 . The structure of claim 1 , wherein the first continuous DT has a maximum width, excluding the air gap, in a range of 1.0 to 1.5 micrometers, and the air gap has a maximum width in a range of 0.2 to 0.5 micrometers.

9 . The structure of claim 1 , wherein the first continuous DT includes a plurality of first continuous DTs that are concentrically arranged.

10 . The structure of claim 1 , wherein the first continuous DT extends vertically along an entirety of a back-end-of-line (BEOL) interconnect stack in the IC region.

11 . The structure of claim 1 , wherein the peripheral region is devoid of any other moisture barrier or crack stop structures other than the air gap in the first dielectric liner.

12 . A protective moisture barrier and crack stop structure for an integrated circuit (IC) chip including an IC region, a peripheral region around the IC region and a back-end-of-line (BEOL) interconnect stack in the IC chip, the structure comprising:
a first continuous deep trench (DT) defined in the peripheral region around the IC region; and an air gap defined by a first dielectric liner in the first continuous DT, wherein the first continuous DT extends vertically along an entirety of the BEOL interconnect stack in the IC region, wherein the peripheral region is devoid of any other moisture barrier or crack stop structures.

13 . The protective moisture barrier and crack stop structure of claim 12 , further comprising:
a second continuous deep trench (DT) defined in a scribe region of the peripheral region around the first continuous DT; and a second dielectric liner in the second continuous DT, wherein the second continuous DT has an open upper end, wherein the first continuous DT has a maximum width smaller than that of the second continuous DT.

14 . The protective moisture barrier and crack stop structure of claim 13 , further comprising a segmented metal seal ring between the first continuous DT and the second continuous DT.

15 . The protective moisture barrier and crack stop structure of claim 12 , wherein the first continuous DT has a maximum width, excluding the air gap, in a range of 1.0 to 1.5 micrometers, and the air gap has a maximum width in a range of 0.2 to 0.5 micrometers.

16 . The protective moisture barrier and crack stop structure of claim 12 , wherein the first continuous DT includes a plurality of first continuous DTs with the air gap therein that are concentrically arranged.

17 . A method, comprising:
in a semiconductor substrate including a plurality of integrated circuit (IC) chips, each IC chip including an IC region and a peripheral region around the IC region, wherein the IC region includes a back-end-of-line (BEOL) interconnect stack:
forming a first continuous deep trench (DT) defined in the peripheral region around the IC region, wherein the first continuous DT extends vertically along an entirety of the BEOL interconnect stack in the IC region; and
forming a dielectric layer over the semiconductor substrate, the dielectric layer forming also forming an air gap in a first dielectric liner in the first continuous DT.

18 . The method of claim 17 , further comprising:
forming a second continuous deep trench (DT) defined in the peripheral region around the first continuous DT, and wherein forming the dielectric layer forms a second dielectric liner in the second continuous DT, wherein the second continuous DT has an open upper end.

19 . The method of claim 18 , further comprising forming a segmented metal seal ring between the first continuous DT and the second continuous DT.

20 . The method of claim 17 , wherein forming the first continuous DT includes forming a plurality of first continuous DTs that are concentrically arranged.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Xiaodong
• Yi Wanbing
• Qiu Weichu

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title