Memory device including conductive contacts in treated tiers

Patent metadata

Field	Value
Publication number	US-2025372168-A1
Application number	US-202519224077-A
Country	US
Kind code	A1
Filing date	May 30, 2025
Priority date	May 31, 2024
Publication date	Dec 4, 2025
Grant date	—

Abstract

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device, which includes levels of dielectric materials; levels of conductive materials interleaved with the levels of dielectric materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending in a direction from the first conductive level to the second conductive level, the second conductive level including a side wall; and a conductive contact extending in the direction from the first conductive level to the second conductive level, the conductive contact including a first portion separated from the first conductive level by a dielectric material, and a second portion adjacent the side wall of the second conductive level.

First claim

What is claimed is:

1 . An apparatus comprising:
levels of dielectric materials; levels of conductive materials interleaved with the levels of dielectric materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending in a direction from the first conductive level to the second conductive level, the second conductive level including a side wall; a conductive contact extending in the direction from the first conductive level to the second conductive level, the conductive contact including a first portion separated from the first conductive level by a dielectric material, and a second portion adjacent the side wall of the second conductive level.

2 . The apparatus of claim 1 , further comprising an additional conductive contact extending in the direction from the first conductive level to the second conductive level, wherein the first conductive level includes a side wall, and the additional conductive contact includes a portion adjacent the side wall of the first conductive level.

3 . The apparatus of claim 2 , further comprising a dielectric pillar between the conductive contact and the additional conductive contact, the dielectric pillar extending in the direction from the first conductive level to the second conductive level.

4 . The apparatus of claim 3 , further comprising an additional dielectric pillar extending in the direction from the first conductive level to the second conductive level, wherein the additional conductive contact is between the dielectric pillar and the additional dielectric pillar.

5 . The apparatus of claim 1 , wherein:
the levels of conductive materials include a third conductive level, and the second conductive level is between the first conductive level and the third conductive level; and the third conductive level includes a first portion, a second portion, and a third portion, the second portion being between the first portion and the third portion, wherein the second portion includes a material different from a material of each of the first portion and the third portion.

6 . The apparatus of claim 1 , wherein the second conductive level is part of a word line associated with the memory cell string.

7 . The apparatus of claim 1 , wherein the conductive contact includes a first conductive material contacting the side wall of the second conductive level, and a second conductive material adjacent the first conductive material.

8 . The apparatus of claim 1 , wherein the second conductive level includes a first conductive material contacting the conductive contact, and a second conductive material adjacent the first conductive material.

9 . The apparatus of claim 1 , wherein:
the conductive contact includes a first conductive material contacting the side wall of the second conductive level, and a second conductive material adjacent the first conductive material; and the second conductive level includes a third conductive material contacting the first conductive material, wherein the first conductive material and the third conductive material include different materials.

10 . The apparatus of claim 1 , wherein:
the conductive contact includes a first conductive material contacting the side wall of the second conductive level; and the second conductive level includes a second conductive material contacting the first conductive material, wherein the first conductive material and the second conductive material include different materials.

11 . An apparatus comprising:
a first tier including first memory cells and a first control gate associated with the first memory cells; a second tier including second memory cells and a second control gate associated with the second memory cells; and a conductive contact extending in a direction from the first control gate to the second control gate, the conductive contact including a first portion separated from the first control gate by a dielectric material, and a second portion contacting a side wall of the second control gate.

12 . The apparatus of claim 11 , further comprising an additional conductive contact extending in the direction from the first control gate to the second control gate, wherein the first control gate includes a side wall, and the additional conductive contact includes a second portion adjacent the side wall of the first control gate.

13 . The apparatus of claim 12 , further comprising a dielectric pillar between the conductive contact and the additional conductive contact, the dielectric pillar extending in the direction from the first control gate to the second control gate.

14 . The apparatus of claim 11 , wherein the second control gate includes a first conductive material adjacent the conductive contact and a second conductive material adjacent the first conductive material.

15 . The apparatus of claim 14 , wherein the conductive contact includes third conductive material adjacent the first conductive material of the conductive contact, and a fourth conductive material adjacent the third conductive material.

16 . The apparatus of claim 15 , wherein:
at least one of the first conductive material and the third conductive material includes titanium nitride; and at least one of the second conductive material and the fourth conductive material includes tungsten.

17 . A method comprising:
forming levels of first dielectric materials and forming levels of second dielectric materials interleaved with the levels of first dielectric materials; forming memory cells including forming a pillar associated with the memory cells through the levels of first dielectric materials and the levels of second dielectric materials; forming a third material at a location in one of the levels of second dielectric materials; replacing the levels of second dielectric materials with levels of conductive materials; removing the third material from the location in one of the levels of second dielectric materials; and forming a conductive contact including forming a portion of the conductive contact in the location in one of the levels of second dielectric materials.

18 . The method of claim 17 , further comprising:
forming a contact opening in the levels of first dielectric materials and the levels of second dielectric materials; forming a dielectric liner in the contact opening, such that the dielectric liner includes a bottom positioned over the location in one of the levels of second dielectric materials, wherein the third material is formed after forming the dielectric liner.

19 . The method of claim 18 , further comprising:
removing a portion of the bottom of the dielectric liner, wherein the third material is formed after removing the portion of the bottom of the dielectric liner.

20 . The method of claim 17 , wherein forming the pillar associated with the memory cells includes:
forming a first opening through a first deck of materials; forming a second deck of materials over the first deck of materials; forming a second opening through the second deck of materials; and forming the pillar at the first opening and the second opening.

Assignees

• Micron Technology Inc

Inventors

• Gupta Sidhartha
• King Matthew J
• Hill Richard J
• Wang Yucheng
• Wang Yiping
• Meldrim John Mark

Classifications

• H10W20/033

  in openings in dielectrics · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title