Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2025365933-A1
Application number	US-202519021642-A
Country	US
Kind code	A1
Filing date	Jan 15, 2025
Priority date	May 22, 2024
Publication date	Nov 27, 2025
Grant date	—

Abstract

A semiconductor device includes: first and second active patterns on a bit line structure; a cell gate structure between the first and second active patterns; and a separation structure between the bit line structure and the cell gate structure. The cell gate structure includes: first and second gate electrodes adjacent to the first and second active patterns, respectively; an insulating layer between the first and second gate electrodes; and a gate dielectric layer on the first and second gate electrodes and the insulating layer. The gate dielectric layer includes: a first vertical portion between the first active pattern and the first gate electrode; a second vertical portion between the second active pattern and the second gate electrode; and an intermediate portion connected to the first and second vertical portions. The separation structure includes: liners between the intermediate portion and the bit line structure; and a capping layer between the liners.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a bit line structure; a first active pattern and a second active pattern on the bit line structure and spaced apart from each other in a first direction parallel to an upper surface of the bit line structure; a cell gate structure between the first active pattern and the second active pattern; and a first separation structure between the bit line structure and the cell gate structure, wherein the cell gate structure comprises:
a first gate electrode adjacent to the first active pattern;
a second gate electrode adjacent to the second active pattern;
an insulating layer between the first and second gate electrodes; and
a gate dielectric layer on the first and second gate electrodes and at least a portion of the insulating layer;
wherein the gate dielectric layer comprises:
first and second vertical portions, the first vertical portion between the first active pattern and the first gate electrode, and the second vertical portion between the second active pattern and the second gate electrode; and
a first intermediate portion connected to the first and second vertical portions and between the first and second gate electrodes and the first separation structure, and
wherein the first separation structure comprises:
first liners spaced apart from each other in the first direction between the first intermediate portion of the gate dielectric layer and the bit line structure; and
a first capping layer between the first liners.

2 . The semiconductor device of claim 1 , wherein each of the first and second active patterns comprises:
a first source/drain region electrically connected to the bit line structure; a second source/drain region on a level higher than a level of the first source/drain region, relative to the upper surface of the bit line structure; and a vertical channel region between the first and second source/drain regions.

3 . The semiconductor device of claim 2 , wherein at least a portion of the vertical channel region faces the first and second gate electrodes.

4 . The semiconductor device of claim 1 , wherein the gate dielectric layer and the first liners of the first separation structure comprise an oxide, and
the first capping layer of the first separation structure comprises a nitride.

5 . The semiconductor device of claim 1 , wherein a thickness of the gate dielectric layer in a second direction perpendicular to the upper surface of the bit line structure is different from a thickness in the first direction of each of the first liners of the first separation structure.

6 . The semiconductor device of claim 1 , wherein an upper surface of the first separation structure is convex toward the upper surface of the bit line structure, and
the first intermediate portion of the gate dielectric layer is convex toward the upper surface of the bit line structure.

7 . The semiconductor device of claim 6 , wherein lower regions of the first and second gate electrodes and a lower region of the insulating layer have a convex shape toward the upper surface of the bit line structure.

8 . The semiconductor device of claim 1 , wherein upper surfaces of the first and second gate electrodes are convex toward the first separation structure.

9 . The semiconductor device of claim 1 , wherein the gate dielectric layer, the first liners, and the first capping layer comprise an oxide.

10 . The semiconductor device of claim 1 , wherein a width of each of the first liners of the first separation structure in the first direction decreases as a distance in a second direction, perpendicular to the upper surface of the bit line structure, from the first intermediate portion of the gate dielectric layer increases.

11 . The semiconductor device of claim 10 , wherein a lower surface of each of the first liners are in contact with the upper surface of the bit line structure.

12 . The semiconductor device of claim 1 , wherein a vertical distance from the upper surface of the bit line structure to lower surfaces of the first and second gate electrodes ranges from 10 nm to 100 nm.

13 . The semiconductor device of claim 1 , wherein a vertical height of the first separation structure, relative to the upper surface of the bit line structure as a reference, ranges from 10 nm to 90 nm.

14 . The semiconductor device of claim 1 , further comprising:
a third active pattern on the bit line structure and spaced apart from the second active pattern in the first direction; a back gate structure between the second active pattern and the third active pattern; and a second separation structure between the bit line structure and the back gate structure, wherein the back gate structure comprises:
a back gate electrode; and
a back gate dielectric layer on at least a portion of the back gate electrode,
wherein the back gate dielectric layer comprises:
third and fourth vertical portions, the third vertical portion between the second active pattern and the back gate electrode and the fourth vertical portion between the third active pattern and the back gate electrode; and
a second intermediate portion connected to the third and fourth vertical portions and between the back gate electrode and the second separation structure, and
wherein the second separation structure comprises:
second liners spaced apart from each other in the first direction between the second intermediate portion of the back gate dielectric layer and the bit line structure; and
a second capping layer between the second liners.

15 . The semiconductor device of claim 14 , wherein a thickness of the back gate dielectric layer in a second direction perpendicular to the upper surface of the bit line structure is different from a thickness in the first direction of each of the second liners of the second separation structure.

16 . A semiconductor device, comprising:
a first vertical active pattern and a second vertical active pattern spaced apart from each other; a gate structure between the first and second vertical active patterns; and an insulating structure on the gate structure, wherein the gate structure comprises:
at least one gate electrode;
an insulating layer on the at least one gate electrode; and
a gate dielectric layer on the at least one gate electrode and at least a portion of the insulating layer,
wherein the gate dielectric layer comprises:
a first portion between the first vertical active pattern and the at least one gate electrode;
a second portion between the second vertical active pattern and the at least one gate electrode; and
a third portion connected to the first and second portions and between the at least one gate electrode and the insulating structure, and
wherein the insulating structure comprises:
liners spaced apart from each other on the third portion of the gate dielectric layer; and
a capping layer between the liners.

17 . The semiconductor device of claim 16 , wherein the at least one gate electrode of the gate structure comprises a plurality of cell gate electrodes,
wherein the plurality of cell gate electrodes comprises:
a first cell gate electrode adjacent to the first vertical active pattern; and
a second cell gate electrode adjacent to the second vertical active pattern, and
wherein the insulating layer of the gate structure is between the first and second cell gate electrodes, the first portion of the gate dielectric layer is between the first vertical active pattern and the first cell gate electrode, the second portion is between the second v

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyunjin
• Kim Donghyung
• Kim Minsoo
• Kim Seungmuk
• Kim Yongkwan
• Kim Jongmin
• Kim Huijung
• Park Jiho

Classifications

• H10B12/05

  Making the transistor · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/482

  Bit lines · CPC title