Post cmp processing for hybrid bonding

Patent metadata

Field	Value
Publication number	US-2025364481-A1
Application number	US-202519284553-A
Country	US
Kind code	A1
Filing date	Jul 29, 2025
Priority date	Jul 26, 2018
Publication date	Nov 27, 2025
Grant date	—

Abstract

Devices and techniques include process steps for forming openings through stacked and bonded structures. The openings are formed by pre-etching through one or more layers of prepared dies after planarization of the bonding layer (by chemical-mechanical polishing (CMP) or the like) and prior to bonding. For instance, the openings are etched through one or more layers of dies to be bonded prior to bonding the dies to form an assembly.

First claim

1 . (canceled)

2 . A microelectronic assembly, comprising:
a first substrate in a first component having a bonding surface with a planarized topography; a first plurality of electrically conductive features at the bonding surface of the first component, wherein the first plurality of electrically conductive feature comprise dummy pads; a second substrate in a second component, the second component having a bonding surface, wherein the bonding surface of the second component has a planarized topography and is direct hybrid bonded to the bonding surface of the first component; a second plurality of electrically conductive features at the bonding surface of the second component and bonded to the first plurality of electrically conductive features; one or more electrically conductive contact pads disposed within an insulating layer of the second component and below the bonding surface of the second component, the one or more electrically conductive contact pads disposed in an area different from the first plurality of electrically conductive features and the second plurality of electrically conductive features; and one or more secondary openings in the insulating layer of the second component aligned to the one or more electrically conductive contact pads, the one or more secondary openings extending from the bonding surface of the second component to the one or more electrically conductive contact pads, providing electrical access to the one or more electrically conductive contact pads, wherein the secondary openings are laterally within a perimeter of the first component and the first and second plurality of electrically conductive features are laterally outside of the secondary openings.

3 . The microelectronic assembly of claim 2 , further comprising one or more primary openings in an insulating layer of the first component, aligned to the one or more secondary openings and to the electrically conductive contact pads, the one or more primary openings extending to the one or more secondary openings, providing electrical access to the one or more electrically conductive contact pads.

4 . The microelectronic assembly of claim 3 , wherein the one or more primary openings have a footprint with a different size and/or shape than the one or more secondary openings.

5 . The microelectronic assembly of claim 3 , further comprising one or more tertiary openings in a base layer of the first substrate, aligned to the one or more primary openings in the insulating layer of the first substrate and to the electrically conductive contact pads, the one or more tertiary openings extending from an outside surface of the first substrate to the one or more primary openings, providing electrical access to the one or more electrically conductive contact pads from beyond the outside surface of the first substrate.

6 . The microelectronic assembly of claim 5 , further comprising one or more electrically conductive structures disposed within one or more of the one or more secondary openings, the one or more primary openings, and the one or more tertiary openings, and electrically coupled to the one or more electrically conductive contact pads.

7 . The microelectronic assembly of claim 6 , further comprising a terminal component coupled to one or more of the electrically conductive structures and configured to provide electrical access to the one or more electrically conductive contact pads from beyond the outside surface of the first substrate.

8 . The microelectronic assembly of claim 6 , wherein one or more of the electrically conductive structures protrudes beyond the outside surface of the first substrate.

9 . The microelectronic assembly of claim 5 , wherein the one or more tertiary openings have a footprint with a different size and/or shape than the one or more primary openings and/or the one or more secondary openings.

10 . The microelectronic assembly of claim 2 , further comprising one or more electrically conductive interconnects electrically coupled to one or more of the electrically conductive contact pads.

11 . The microelectronic assembly of claim 2 , further comprising at least one metal layer disposed on an outside surface of the first substrate configured for electromagnetic interference (EMI) protection and/or for heat dissipation.

12 . The microelectronic assembly of claim 2 , further comprising a protective metal coating disposed on a surface of the one or more electrically conductive contact pads.

13 . The microelectronic assembly of claim 2 , wherein the one or more electrically conductive contact pads are disposed between two or more active areas of the microelectronic assembly and/or within one or more active areas of the microelectronic assembly.

14 . The microelectronic assembly of claim 2 , wherein the electrically conductive features of the second plurality are misaligned to the electrically conductive features of the first plurality by a first extent.

15 . The microelectronic assembly of claim 2 , wherein the first component includes at least one island in an active region of the first component.

16 . The microelectronic assembly of claim 2 , wherein the bonding surface of the first component is bonded to the bonding surface of the second component using an adhesive-less, room temperature, covalent bonding technique.

17 . The microelectronic assembly of claim 2 , wherein a footprint of the first substrate is smaller than a footprint of the second substrate.

18 . A microelectronic assembly, comprising:
a first substrate having a hybrid bonding surface comprising an insulator material with one or more metallic features therein, the hybrid bonding surface having a planarized topography; a second substrate having a hybrid bonding surface comprising an insulator material with one or more metallic features embedded therein, the hybrid bonding surface of the second substrate having a planarized topography and direct hybrid bonded to the hybrid bonding surface of the first substrate, with the one or more metallic features of the second substrate bonded to the one or more metallic features of the first substrate; a cavity disposed at a bond joint between the first substrate and the second substrate where the hybrid bonding surface of the first substrate and the hybrid bonding surface of the second substrate make contact, the cavity formed at least by a recess in the hybrid bonding layer of the first substrate; and a continuous seal formed by the one or more metallic features of the first substrate bonded to the one or more metallic features of the second substrate disposed around a periphery of the cavity at the bond joint; wherein the second substrate includes one or more electrically conductive contact pads disposed at the hybrid bonding surface of the second substrate outside a perimeter of the first substrate, the one or more electrically conductive contact pads configured to electrically interconnect the second substrate to an element other than the first substrate.

19 . The microelectronic assembly of claim 18 , further comprising one or more of a microelectronic component, a circuit, or a sensor disposed within the cavity.

20 . The microelectronic assembly of claim 18 , further comprising a third substrate having a hybrid bonding surface comprising an insulator material with one or more metallic features embedded therein, the hybrid bonding surface of the third substrate having a planarized topography and bonded to the first substrate, with the one or more metallic features of the third substrate

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Fountain Jr Gaius Gillman
• Gao Guilian
• Mandalapu Chandrasekhar

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title