Semiconductor packaging

Patent metadata

Field	Value
Publication number	US-2025357458-A1
Application number	US-202519290834-A
Country	US
Kind code	A1
Filing date	Aug 5, 2025
Priority date	Jun 24, 2022
Publication date	Nov 20, 2025
Grant date	—

Abstract

The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

First claim

What is claimed is:

1 . A method, comprising:
forming an adhesion layer in contact with a top surface of a first semiconductor package and a first joint pad in contact with the adhesion layer, wherein the adhesion layer covers a portion of the top surface of the first semiconductor package and the first joint pad is disposed on the adhesion layer; depositing a film layer on the top surface of the first semiconductor package, wherein a thickness of the film layer is greater than a summation of a thickness of the first joint pad and a thickness of the adhesion layer; etching openings in the film layer, wherein etching the openings comprises forming slanted sidewalls that overlap with a first portion of the first joint pad and expose a second portion of the first joint pad; attaching a solder ball to the second portion of the first joint pad and to a second joint pad of a second semiconductor package; and forming a through-interposer via (TIV) adjacent to the first semiconductor package, wherein:
a depth of the TIV is substantially equal to a summation of a height of the first semiconductor package and a height of the film layer; and
a top surface of the TIV is coplanar with a top surface of the film layer.

2 . The method of claim 1 , wherein forming the TIV comprises:
spin coating a photoresist layer around the first semiconductor package; forming an opening in the photoresist layer by a photolithography process; and filling the opening with a metal.

3 . The method of claim 2 , wherein filling the opening comprises depositing the metal by a chemical vapor deposition process.

4 . The method of claim 1 , wherein forming the adhesion layer and first joint pad comprises forming a joint pad thickness of the first joint pad and an adhesion layer thickness of the adhesion layer to have a ratio between about 10 and about 300 , wherein the joint pad thickness is greater than the adhesion layer thickness.

5 . The method of claim 1 , wherein forming the adhesion layer and first joint pad comprises forming an adhesion layer width of the adhesion layer and a joint pad width of the second portion of the first joint pad between about 1.2 and about 10, wherein the adhesion layer width is greater than the joint pad width.

6 . The method of claim 1 , wherein etching the openings comprises forming the slanted sidewalls with an angle between the slanted sidewalls and a horizontal direction between about 30° and about 80°.

7 . The method of claim 1 , further comprising:
forming a molding layer between the first semiconductor package and the TIV; and forming a filling layer adjacent to the solder ball and between the film layer and the second semiconductor package.

8 . The method of claim 7 , further comprising performing a chemical mechanical planarization process to planarize the top surface of the TIV structure and a top surface of the molding layer.

9 . The method of claim 1 , further comprising forming a redistribution layer and an input/output connection on a bottom surface of the first semiconductor package before forming the adhesion layer.

10 . The method of claim 1 , further comprising:
placing a third semiconductor package, comprising a power management device, adjacent to the first semiconductor package; and electrically coupling the third semiconductor package to the first and second semiconductor packages.

11 . A method, comprising:
forming an adhesion layer in contact with a first semiconductor package; forming a first joint pad in contact with the adhesion layer; forming a film layer on the first semiconductor package and a portion of a top surface of the first joint pad, wherein:
a bottom surface of the film layer is in contact with a top surface of the first semiconductor package and a top surface of the film layer is disposed above the top surface of the first joint pad; and
the film layer comprises a slanted sidewall that overlaps with an end portion of the adhesion layer and a first portion of the first joint pad;
attaching a solder ball to a second portion of the first joint pad and to a second joint pad of a second semiconductor package; and forming a through-interposer via (TIV) structure adjacent to the first semiconductor package, wherein:
a height of the TIV structure is substantially equal to a summation of a height of the first semiconductor package and a height of the film layer; and
a top surface of the TIV structure is coplanar with a top surface of the film layer.

12 . The method of claim 11 , wherein forming the film layer comprises ablating the film layer with a laser milling process to form the slanted sidewall.

13 . The method of claim 11 , wherein forming the first joint pad comprises forming the first joint pad with a thickness between about 0.5 μm and about 300 μm.

14 . The method of claim 11 , wherein forming the first joint pad and the adhesion layer comprises forming a joint pad thickness of the first joint pad and an adhesion layer thickness of the adhesion layer to have a ration between about 10 and about 300, wherein the joint pad thickness is greater than the adhesion layer thickness.

15 . The method of claim 11 , further comprising first forming a redistribution layer and an input/output connection on a bottom surface of the first semiconductor package prior to forming the adhesion layer.

16 . The method of claim 11 , further comprising thinning the first semiconductor package prior to forming the adhesion layer.

17 . A method, comprising:
forming an adhesion layer in contact with a first semiconductor package; forming a first joint pad in contact with the adhesion layer; forming a film layer on the first semiconductor package and the first joint pad, comprising:
forming a slanted sidewall of the film layer;
covering an end portion of the adhesion layer and a first portion of the first joint pad; and
exposing a second portion of the first joint pad; and
forming a ball grid array (BGA) between the second portion of the first joint pad and a second joint pad of a second semiconductor package.

18 . The method of claim 17 , further comprising:
forming a through-interposer via (TIV) structure adjacent to the first semiconductor package; forming a first redistribution layer (RDL) and an input/output (I/O) connection below the first semiconductor package; and forming a second RDL below the I/O connection to electrically couple to the I/O connection and the TIV structure.

19 . The method of claim 18 , further comprising:
filling a space between the TIV structure and the first semiconductor package with a molding layer; and filling a space adjacent to the BGA and between the film layer and the second semiconductor package with a filling layer.

20 . The method of claim 17 , wherein exposing the second portion of the first joint pad comprises removing a portion of the film layer by a laser milling process, a dry etch process, or a wet etch process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tien-Chung
• Huang Li-Hsien
• Wu Ming-Feng
• Chuang Yao-Chun
• He Jun

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title