Semiconductor devices having non-uniform pattern density for hybrid bonding

Patent metadata

Field	Value
Publication number	US-2025357396-A1
Application number	US-202418666789-A
Country	US
Kind code	A1
Filing date	May 16, 2024
Priority date	May 16, 2024
Publication date	Nov 20, 2025
Grant date	—

Abstract

The embodiments herein relate to semiconductor devices having a non-uniform pattern density for hybrid bonding. A semiconductor structure is provided. The semiconductor structure may include a semiconductor device having a substrate, a device region over the substrate, a bonding region over the device region, and a plurality of bonding structures in the bonding region. The bonding region may include a first bonding area having a first pattern density, a second bonding area having a second pattern density adjacent to the first bonding area, and a third bonding area having a third pattern density adjacent to the second bonding area. The plurality of bonding structures in the bonding region may include a first bonding structure in the first bonding area, a second bonding structure in the second bonding area, and a third bonding structure in the third bonding area.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a semiconductor device including:
a substrate;
a device region over the substrate;
a bonding region over the device region, wherein the bonding region includes a first bonding area having a first pattern density, a second bonding area having a second pattern density adjacent to the first bonding area, and a third bonding area having a third pattern density adjacent to the second bonding area; and
a plurality of bonding structures in the bonding region including a first bonding structure in the first bonding area, a second bonding structure in the second bonding area, and a third bonding structure in the third bonding area.

2 . The semiconductor structure of claim 1 , wherein the first pattern density is higher than the second pattern density.

3 . The semiconductor structure of claim 2 , wherein the second pattern density is higher than the third pattern density.

4 . The semiconductor structure of claim 3 , wherein the second bonding structure is electrically floating and does not have electrical functions.

5 . The semiconductor structure of claim 4 , wherein the first and third bonding structures are active bonding structures having electrical functions.

6 . The semiconductor structure of claim 1 , wherein the first, second, and third bonding structures each comprises:
a horizontal line structure; and at least one vertical via structure electrically connected to the line structure.

7 . The semiconductor structure of claim 6 , wherein the line structure of the first, second, and third bonding structures are substantially parallel.

8 . The semiconductor structure of claim 6 , wherein the second bonding area further comprises a fourth bonding structure immediately between the first and second bonding structures, wherein the fourth bonding structure is spaced apart from the first bonding structure by a first distance and from the second bonding structure by a second distance different from the first distance.

9 . The semiconductor structure of claim 8 , wherein the first distance is wider than the second distance.

10 . The semiconductor structure of claim 9 , wherein the first distance is at most two micrometers.

11 . The semiconductor structure of claim 6 , wherein the line structure of the second bonding structure has a length substantially equal to the line structure of the first bonding structure.

12 . The semiconductor structure of claim 6 , wherein the line structure of the second bonding structure has a shorter length than the line structure of the first bonding structure.

13 . The semiconductor structure of claim 12 , wherein the second bonding area further comprises a fourth bonding structure between the first and second bonding structures, wherein the fourth bonding structure has a shorter length than the line structure of the first bonding structure and a longer length than the line structure of the second bonding structure.

14 . The semiconductor structure of claim 6 , wherein the at least one via structure is part of a plurality of via structures, and the plurality of via structures is arranged in an array configuration of rows and columns.

15 . The semiconductor structure of claim 1 , wherein the first bonding area has a first antenna ratio, the second bonding area has a second antenna ratio lower than the first antenna ratio, and the third bonding area has a third antenna ratio lower than the second pattern density.

16 . The semiconductor structure of claim 1 , wherein the semiconductor device is a first semiconductor device, further comprising a second semiconductor device including a fourth bonding structure, a fifth bonding structure, and a sixth bonding structure bonded to the first, second, and third bonding structures, respectively, at a bonding interface.

17 . The semiconductor structure of claim 16 , wherein the second bonding structure is electrically isolated from the first and third bonding structures by a first dielectric layer, and the fifth bonding structure is electrically isolated from the fourth and sixth bonding structures by a second dielectric layer, wherein the first dielectric layer and the second dielectric layer are bonded at the bonding interface.

18 . The semiconductor structure of claim 17 , wherein the bonding interface extends across the semiconductor structure.

19 . The semiconductor structure of claim 16 , wherein the fourth and sixth bonding structures are active bonding structures having electrical functions.

20 . The semiconductor structure of claim 19 , wherein the fifth bonding structure is electrically floating and does not have electrical functions.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Xiaodong
• Yi Wanbing
• Qiu Weichu
• Chen Chung-Shou
• Chong Kelvin Phok Yong
• Dizon Gerardo Gerry Sarcilla

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title