Silicon structure to monitor bitcell performance

Patent metadata

Field	Value
Publication number	US-2025349628-A1
Application number	US-202418657245-A
Country	US
Kind code	A1
Filing date	May 7, 2024
Priority date	May 7, 2024
Publication date	Nov 13, 2025
Grant date	—

Abstract

Silicon wafers including multiple wafer test structures, each comprising a ring oscillator comprising multiple bit-storing cells configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline. The oscillation frequency of the ring oscillator changes in accordance with the discharge rate of the bitlines, which is affected by factors such as word line under-drive and aging. The silicon wafers include at least one frequency monitor coupled to one or more of the ring oscillators.

First claim

What is claimed is:

1 . A circuit comprising:
a frequency monitor coupled to a ring oscillator; and the ring oscillator comprising a plurality of bit-storing cells configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline.

2 . The circuit of claim 1 , the ring oscillator comprising a prime number of stages.

3 . The circuit of claim 1 , wherein the bit-storing cells are Static Random Access Memory (SRAM) cells.

4 . The circuit of claim 3 , wherein the SRAM cells are six-transistor cells.

5 . The circuit of claim 3 , wherein the SRAM cells are eight-transistor cells.

6 . The circuit of claim 1 , further comprising:
pre-charge logic for each of a plurality of stages of the ring oscillator; and wherein the pre-charge logic for each stage of the ring oscillator is configured to activate in response to a bitline sense signal for a previous adjacent stage and a bitline sense signal for a subsequent adjacent stage.

7 . The circuit of claim 1 , further comprising:
calibration logic configured to determine a delay of peripheral logic of the bit-storing cells.

8 . The circuit of claim 7 , the calibration logic configured to:
determine a first oscillation period of the ring oscillator arising from a cumulative delay of discharge of the bit-storing cells and delay introduced by the peripheral logic; and determine a second oscillation period of the ring oscillator arising from a delay of the peripheral logic and not including the delay of discharge of the bit-storing cells.

9 . A silicon wafer comprising:
a plurality of wafer test structures, each of the plurality of wafer test structures comprising a ring oscillator comprising a plurality of bit-storing cells configured such that the discharge of a bitline triggers charging of a first adjacent bitline and discharge of a second adjacent bitline; and at least one frequency monitor coupled to one or more of the ring oscillators.

10 . The silicon wafer of claim 9 , further comprising:
calibration logic configured to determine a delay of peripheral logic of the bit-storing cells.

11 . The silicon wafer of claim 10 , the calibration logic configured to:
determine a first oscillation period of the ring oscillator arising from a cumulative delay of discharge of the bit-storing cells and delay introduced by the peripheral logic; and determine a second oscillation period of the ring oscillator arising from a delay of the peripheral logic and not including the delay of discharge of the bit-storing cells.

12 . The silicon wafer of claim 9 , wherein the bit-storing cells are Static Random Access Memory (SRAM) cells.

13 . The silicon wafer of claim 12 , wherein the SRAM cells are six-transistor cells.

14 . The silicon wafer of claim 12 , wherein the SRAM cells are eight-transistor cells.

15 . The silicon wafer of claim 9 , further comprising:
pre-charge logic for each of a plurality of stages of the ring oscillator; and wherein the pre-charge logic for each stage of the ring oscillator is configured to activate in response to a bitline sense signal for a previous adjacent stage and a bitline sense signal for a subsequent adjacent stage.

16 . A silicon wafer manufacturing process comprising:
forming on the silicon wafer a plurality of ring oscillators each comprising a plurality of bit-storing cells and stages, each of the stages configured such that the discharge of a bitline of the stage triggers charging of a bitline of a first adjacent stage and discharging of a bitline of a second adjacent stage; and forming on the silicon wafer at least one frequency monitor coupled to one or more of the ring oscillators.

17 . The silicon wafer manufacturing process of claim 10 , the calibration logic configured to:
determine a first oscillation period of the ring oscillator arising from a cumulative delay of discharge of the bit-storing cells and delay introduced by the peripheral logic; and determine a second oscillation period of the ring oscillator arising from a delay of the peripheral logic and not including the delay of discharge of the bit-storing cells.

18 . The silicon wafer manufacturing process of claim 9 , wherein each stage comprises pre-charge logic configured to activate in response to a bitline sense signal for a previous adjacent stage and a bitline sense signal for a subsequent adjacent stage.

19 . The silicon wafer of claim 9 , wherein the bit-storing cells are Static Random Access Memory (SRAM) cells.

20 . The silicon wafer of claim 19 , wherein the SRAM cells are one of six-transistor cells and eight transistor cells.

Assignees

• Nvidia Corp

Inventors

• Patel Manish Umedlal
• Balakrishnan Karthik

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10B10/00

  Static random access memory [SRAM] devices · CPC title

• G01R23/02 Primary

  Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage · CPC title

• H01L22/34 Primary

  Electricity · mapped topic