Transistor gate contacts

Patent metadata

Field	Value
Publication number	US-2025349607-A1
Application number	US-202519277068-A
Country	US
Kind code	A1
Filing date	Jul 22, 2025
Priority date	Mar 26, 2021
Publication date	Nov 13, 2025
Grant date	—

Abstract

In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

First claim

1 . (canceled)

2 . A method comprising:
forming a first contact opening through a gate mask to expose a gate structure and a gate spacer, the gate spacer disposed along a sidewall of the gate structure and along a sidewall of the gate mask; after forming the first contact opening, extending the first contact opening along the sidewall of the gate structure; forming a contact spacer in an upper portion of the first contact opening over the gate structure, the contact spacer sealing a lower portion of the first contact opening along the sidewall of the gate structure; and forming a gate contact in the upper portion of the first contact opening, the gate contact physically contacting the gate structure, the contact spacer disposed around the gate contact.

3 . The method of claim 2 further comprising:
growing a source/drain region adjacent to a channel region, the gate structure disposed over the channel region;
depositing a first inter-layer dielectric over the source/drain region;
forming a second contact opening through the first inter-layer dielectric to expose the source/drain region, the gate mask covering the gate structure while forming the second contact opening; and
forming a lower source/drain contact in the second contact opening, the lower source/drain contact physically contacting the source/drain region.

4 . The method of claim 3 , wherein top surfaces of the lower source/drain contact, the gate mask, and the gate spacer are coplanar.

5 . The method of claim 3 further comprising:
forming a contact mask over the lower source/drain contact, top surfaces of the contact mask, the gate mask, and the gate spacer being coplanar.

6 . The method of claim 3 further comprising:
depositing a second inter-layer dielectric over the lower source/drain contact, the gate mask, and the gate spacer, wherein the first contact opening is also formed through the second inter-layer dielectric; and
before extending the first contact opening, widening the first contact opening to expose the lower source/drain contact.

7 . The method of claim 2 , wherein the sidewall of the gate structure is free of the contact spacer.

8 . The method of claim 2 , wherein the sidewall of the gate structure physically contacts the contact spacer.

9 . The method of claim 2 , wherein forming the first contact opening comprises performing an anisotropic etching process, and extending the first contact opening comprises performing an isotropic etching process.

10 . The method of claim 9 , wherein the gate mask comprises silicon nitride, and the anisotropic etching process is a dry etch performed with carbon tetrafluoride.

11 . The method of claim 9 , wherein the gate spacer comprises silicon nitride, and the isotropic etching process is a wet etch performed with phosphoric acid.

12 . The method of claim 2 further comprising:
growing a source/drain region adjacent to a channel region, the gate structure disposed over the channel region;
depositing a first inter-layer dielectric over the source/drain region;
forming a second contact opening through the first inter-layer dielectric to expose the source/drain region, the gate mask covering the gate structure while forming the second contact opening;
forming a lower source/drain contact in the second contact opening, the lower source/drain contact physically contacting the source/drain region;
forming a contact mask over the lower source/drain contact;
depositing a second inter-layer dielectric over the contact mask, the gate mask, and the gate spacer, wherein the first contact opening is also formed through the second inter-layer dielectric;
before extending the first contact opening, widening the first contact opening to expose the contact mask; and
extending the first contact opening through the contact mask to expose the lower source/drain contact.

13 . A method comprising:
forming a contact opening through an etch stop layer to expose a gate structure and a gate spacer, the gate spacer disposed along a sidewall of the gate structure; after forming the contact opening, extending the contact opening along the sidewall of the gate structure; forming a contact spacer in an upper portion of the contact opening over the gate structure, the contact spacer sealing a lower portion of the contact opening along the sidewall of the gate structure; and forming a gate contact in the upper portion of the contact opening, the gate contact physically contacting the gate structure, the contact spacer disposed around the gate contact.

14 . The method of claim 13 , wherein forming the contact spacer comprises:
depositing a spacer layer in the upper portion of the contact opening; and patterning the spacer layer to remove a horizontal portion of the spacer layer over the gate structure.

15 . The method of claim 13 , wherein the contact spacer extends through the etch stop layer.

16 . The method of claim 13 , wherein the sidewall of the gate structure is free of the contact spacer.

17 . The method of claim 13 , wherein the sidewall of the gate structure physically contacts the contact spacer.

18 . The method of claim 13 , wherein forming the contact opening comprises performing an anisotropic etching process, and extending the contact opening comprises performing an isotropic etching process.

19 . The method of claim 13 , further comprising:
widening the contact opening to expose a source/drain contact, the source/drain contact physically contacting a source/drain region, the source/drain region adjacent to a channel region, the gate structure disposed over the channel region.

20 . A method comprising:
forming a contact opening through an etch stop layer to expose a gate structure and a gate spacer, the gate spacer disposed between the gate structure and a source/drain region; widening the contact opening to expose a source/drain contact, the source/drain contact physically contacting the source/drain region; extending the contact opening between the gate structure and the source/drain region; forming a contact spacer in an upper portion of the contact opening over the gate structure, the contact spacer sealing a lower portion of the contact opening between the gate structure and the source/drain region; and forming a gate contact in the upper portion of the contact opening, the gate contact physically contacting the gate structure and the source/drain contact.

21 . The method of claim 20 , wherein forming the contact opening comprises performing an anisotropic etching process, and extending the contact opening comprises performing an isotropic etching process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Chui Chi On

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title