Chip testing device and chip testing method

Patent metadata

Field	Value
Publication number	US-2025347717-A1
Application number	US-202519273158-A
Country	US
Kind code	A1
Filing date	Jul 18, 2025
Priority date	Jan 20, 2023
Publication date	Nov 13, 2025
Grant date	—

Abstract

Embodiments of the present application provide a chip testing device and a method for testing chips. The device has a processor that can read information about how and in what order to connect certain pins of a chip to a power source. Based on that information, the processor controls the connections to follow the correct sequence. This approach helps make chip testing faster and more efficient.

First claim

What is claimed is:

1 . A chip testing device, comprising: a processor configured to acquire pin connection control information of a target chip, the pin connection control information being used for indicating a sequence of connection between at least some pins of the target chip and a power supply module; and
further configured to control the at least some pins to be connected to the power supply module according to the sequence of connection.

2 . The chip testing device according to claim 1 , wherein the power supply module comprises a plurality of power supply units, and the processor is specifically configured to:
control the at least some pins to be connected respectively to positive and negative electrodes of at least some of the plurality of power supply units according to the sequence of connection.

3 . The chip testing device according to claim 2 , wherein the at least some power supply units comprise a first power supply unit and a second power supply unit, and the processor is specifically configured to:
control two pins among the at least some pins to be connected respectively to a positive electrode of the first power supply unit and a negative electrode of the second power supply unit according to the sequence of connection, so that the voltage between the two pins is U, wherein U is a sum of the voltages of the plurality of power supply units.

4 . The chip testing device according to claim 3 , wherein the sequence of connection comprises: the two pins are connected to the power supply module first, wherein the sequence of connection further comprises: after the two pins are connected to the power supply module, the pins among the at least some pins except the two pins are connected to the power supply module in a random sequence.

5 . The chip testing device according to claim 1 further comprises a switch matrix, through which the pins of the target chip are connected to the power supply module, and the pin connection control information is used for indicating a switch closing sequence of the switch matrix.

6 . The chip testing device according to claim 5 , wherein the power supply module comprises a first power supply submodule and a second power supply submodule, the target chip comprises a first target chip and a second target chip, the switch matrix comprises a plurality of first switches, a plurality of second switches, a first connector, a second connector, a third connector and a fourth connector, the first connector is connected to the first power supply submodule, the second connector is connected to the second power supply submodule, the third connector is connected to the first target chip, the fourth connector is connected to the second target chip, the first connector and the third connector are connected through the plurality of first switches, the second connector and the fourth connector are connected through the plurality of second switches, the power pin and the ground pin of the first target chip are connected respectively to a positive electrode and a negative electrode of the first power supply submodule, and the power pin and the ground pin of the second target chip are connected respectively to a positive electrode and a negative electrode of the second power supply submodule.

7 . The chip testing device according to claim 6 , wherein the switch closing sequence comprises: two first switches among the plurality of first switches connected to the power pin and the ground pin of the first target chip are closed first, and then the other first switches among the plurality of first switches are randomly closed; and/or
two second switches among the second switches connected to the power pin and the ground pin of the second target chip are closed first, and then the other second switches among the plurality of second switches are randomly closed.

8 . The chip testing device according to claim 6 , wherein the switch closing sequence comprises: the plurality of first switches are randomly closed, and/or the plurality of second switches are randomly closed.

9 . The chip testing device according to claim 5 , wherein the power supply module comprises a first power supply submodule and a second power supply submodule connected in series, the target chip comprises a first target chip or a second target chip, the switch matrix comprises a plurality of third switches, a first connector, a second connector and a third connector, the first connector is connected to the first power supply submodule, the second connector is connected to the second power supply submodule, the third connector is connected to the first target chip or the second target chip, and the first connector and the second connector are connected to the third connector through the plurality of third switches.

10 . The chip testing device according to claim 9 , wherein the switch closing sequence comprises: a first group of the third switches connected to the first connector are closed first, followed by the closure of a second group of third switches connected to the second connector; or
a first group of the third switches connected to the second connector are closed first, and then a second group of the third switches connected to the first connector are closed.

11 . The chip testing device according to claim 10 , wherein the power pin and the ground pin of the first target chip or the second target chip are connected respectively to the positive electrode and the negative electrode of the power supply module;
the first group of the third switches comprise a switch connected to the power pin of the first target chip or the second target chip, and the second group of the third switches comprise a switch connected to the ground pin of the first target chip or the second target chip, and the switch closing sequence comprises: after the first group of the third switches are closed, the switch in the second group of the third switches connected to the ground pin of the first target chip or the second target chip is closed first, and then the other third switches among the second group of the third switches are randomly closed; or the first group of the third switches comprise a switch connected to the ground pin of the first target chip or the second target chip, and the second group of the third switches comprise a switch connected to the power pin of the first target chip or the second target chip, and the switch closing sequence comprises: after the first group of the third switches are closed, the switch in the second group of the third switches connected to the power pin of the first target chip or the second target chip is closed first, and then the other switches in the second group of the third switches are randomly closed.

12 . The chip testing device according to claim 5 , wherein the target chip comprises a first target chip and a second target chip, the switch matrix comprises a plurality of fourth switches, a plurality of fifth switches, a first connector and a second connector, the first connector is connected to the power supply module, the first target chip and the second target chip are both connected to the second connector, the first connector and the second connector are connected through the plurality of fourth switches and the plurality of fifth switches, the power pin and the ground pin of the first target chip are connected respectively to the positive electrode and the negative electrode of some power supply units in the power supply module, and the power pin and the ground pin of the second target chip are connected respectively to the positive electrode and the negative electrode of the other some power supply units in the power supply module.

Assignees

• Contemporary Amperex Technology Co Ltd

Inventors

• Zhou Fangjie
• Wang Xingchang
• Li Qiandeng

Classifications

• G01R31/31724 Primary

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• G01R31/2886

  Features relating to contacting the IC under test, e.g. probe heads; chucks (G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06) · CPC title

• G01R31/01

  Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station (testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12) · CPC title

• G01R31/2879 Primary

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title