Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025344386-A1
Application number	US-202519271347-A
Country	US
Kind code	A1
Filing date	Jul 16, 2025
Priority date	Jan 6, 2022
Publication date	Nov 6, 2025
Grant date	—

Abstract

Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of memory blocks formed on a source line, the plurality of memory blocks separated by a slit, a source contact formed in the slit, a plurality of normal bit lines arranged, in parallel, over the memory blocks, the plurality of normal bit lines being spaced apart in a first direction and extending in a second direction, a plurality of dummy groups disposed between the plurality of normal bit lines, each of the plurality of dummy groups including dummy bit lines, a first dummy pad extending in the first direction and contacting end portions of the dummy groups, a first upper contact formed on the first dummy pad, and a lower contact formed between the dummy bit lines and the source contact.

First claim

What is claimed is:

1 . A method of manufacturing a memory device, comprising:
forming memory blocks disposed on a source line and separated from each other by a slit; forming a source contact in the slit; forming a first interlayer insulating layer and a lower contact overlapping with areas of the memory blocks and the source contact; forming a first pattern on the first interlayer insulating layer and the lower contact, the first pattern being configured to expose portions of the first interlayer insulating layer and the lower contact through main openings and dummy openings, the dummy openings having a length that is shorter than a length of the main openings; forming first spacers on side surfaces of the first pattern; removing the first pattern and allowing the first spacers to remain; forming second spacers on side surfaces of the first spacers; removing the first spacers and allowing the second spacers to remain; forming a bit line pattern between the second spacers; forming normal bit lines and dummy bit lines by removing the second spacers; forming an upper contact on a portion of the bit line pattern that is wider than the remaining portions of the bit line pattern; and forming a conductive layer, to which the source voltage is provided, on the upper contact.

2 . The method according to claim 1 , wherein forming the first interlayer insulating layer and the lower contact comprises:
forming the first interlayer insulating layer on an entire area of the memory device; forming a contact hole in the first interlayer insulating layer such that a portion of the source contact is exposed; and forming the lower contact that contacts the source contact by filling the contact hole with a conductive material.

3 . The method according to claim 1 , wherein, in the first pattern, the main openings are formed in a region in which the normal bit lines are to be formed, and the dummy openings are formed in a region in which the dummy bit lines are to be formed,
wherein the dummy openings are between the main openings.

4 . The method according to claim 1 , wherein the first spacers are formed of a material having an etch selectivity that is different from an etch selectivity of the first pattern.

5 . The method according to claim 1 , wherein the second spacers are formed of a material having an etch selectivity that is different from an etch selectivity of the first spacers.

6 . The method according to claim 1 , wherein the bit line pattern is formed of a conductive layer or a metal layer.

7 . The method according to claim 1 , wherein the portions of the bit line pattern that remain after removing the second spacers form the normal bit lines and the dummy bit lines.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10B41/10 Primary

  characterised by the top-view layout · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title