Selective cap deposition on graphene-capped conductive lines

Patent metadata

Field	Value
Publication number	US-2025343147-A1
Application number	US-202418653195-A
Country	US
Kind code	A1
Filing date	May 2, 2024
Priority date	May 2, 2024
Publication date	Nov 6, 2025
Grant date	—

Abstract

Disclosed herein are integrated circuit (IC) structures fabricated with selective cap deposition techniques on graphene-capped conductive lines and IC structures and devices with graphene on capped conductive lines. In one example, an IC structure includes an interconnect layer with a conductive line, a conductive cap layer over the conductive line, and a layer of graphene between the conductive line and the conductive cap or a layer of graphene over the conductive cap. In one such example, the layer of graphene may enable lower resistance in the conductive line and the conductive cap may improve electromigration reliability.

First claim

1 . An integrated circuit (IC) structure, comprising:
a device region; and an interconnect layer over the device region, wherein the interconnect layer includes:
a conductive line including a first conductive material, a conductive layer over the conductive line, wherein the conductive layer includes a second conductive material, an insulator layer over the conductive layer, and a layer between the conductive line and the insulator layer, wherein the layer includes carbon atoms arranged in a hexagonal lattice.

2 . The IC structure of claim 1 , wherein:
the layer including the carbon atoms arranged in a hexagonal lattice includes a monolayer of graphene; and the monolayer of graphene is between the first conductive material and the second conductive material.

3 . The IC structure of claim 1 , wherein:
the layer including the carbon atoms arranged in a hexagonal lattice includes a monolayer of graphene; and the second conductive material is between the first layer of conductive material and the monolayer of graphene.

4 . The IC structure of claim 1 , wherein:
the interconnect layer is a first interconnect layer, the conductive line is a first conductive line, the conductive layer is a first conductive layer, the insulator layer is a first insulator layer, and the layer is a first layer; the IC structure includes a second interconnect layer over the first interconnect layer; and the second interconnect layer includes:
a second conductive line including the first conductive material, a second conductive layer over the second conductive line, wherein the second conductive layer includes the second conductive material, a second insulator layer over the second conductive layer, and a second layer between the second conductive line and the second insulator layer, wherein the second layer includes carbon atoms arranged in a hexagonal lattice.

5 . The IC structure of claim 4 , wherein:
the IC structure includes a third interconnect layer between the first interconnect layer and the second interconnect layer; the third interconnect layer includes a third conductive interconnect; and carbon is absent between the third conductive interconnect and the second conductive interconnect.

6 . The IC structure of claim 1 , wherein:
the interconnect layer includes an insulator material; the conductive line is in an opening in an insulator material; the IC structure includes a liner on sidewalls of the opening; and the second conductive material is in contact with the liner.

7 . The IC structure of claim 1 , wherein:
the layer including the carbon atoms arranged in a hexagonal lattice has a first thickness, wherein the first thickness is a dimension of the layer in a plane substantially orthogonal to the device region; the conductive layer has a second thickness, wherein the second thickness is a dimension of the conductive layer in the plane; and the second thickness is about 1.5 to 3 times greater than the first thickness.

8 . The IC structure of claim 1 , wherein:
the layer has a thickness in a range of 8-12 Angstrom, wherein the thickness is a dimension of the layer in a plane substantially orthogonal to the device region.

9 . The IC structure of claim 1 , wherein:
the first conductive material includes copper; the layer including the carbon atoms arranged in a hexagonal lattice includes a monolayer of graphene on the copper; and the conductive layer includes cobalt on the monolayer of graphene.

10 . The IC structure of claim 1 , wherein:
the interconnect layer is a first interconnect layer and the conductive line includes a first conductive line; and the IC structure includes:
a second interconnect layer over the first interconnect layer, wherein the second interconnect layer includes a second conductive line, and a conductive via between the first conductive line and the second conductive line; and
the layer including the carbon atoms arranged in a hexagonal lattice is between the first conductive line and the conductive via.

11 . An integrated circuit (IC) structure, comprising:
a front end of line (FEOL) layer; and a back end of line (BEOL) layer over the FEOL layer, wherein the BEOL layer includes:
an insulator material, a conductive line in an opening in the insulator material, wherein the conductive line includes a first conductive material, a liner on sidewalls of the opening, a material including carbon over the first conductive material, and a second conductive material over the material including carbon and over the liner.

12 . The IC structure of claim 11 , wherein:
the material includes graphene.

13 . The IC structure of claim 11 , wherein:
the material including carbon is absent between the liner on the sidewalls of the opening and the second conductive material.

14 . The IC structure of claim 11 , wherein:
the second conductive material includes a conductive cap material having a first thickness; the material including carbon has a second thickness; and the first thickness is greater than the second thickness.

15 . A method of fabricating an integrated circuit (IC) structure, the method comprising:
providing a preliminary IC structure including a device region and a layer over the device region that includes a conductive line in an opening in an insulator material, wherein the conductive line includes a first conductive material; providing a layer of graphene over the conductive line; and providing a second conductive material over the graphene.

16 . The method of claim 15 , further comprising:
prior to providing the second conductive material over the layer of graphene, plasma treating the layer of graphene with a hydrogen plasma, an oxygen plasma, or an ammonia plasma.

17 . The method of claim 15 , wherein:
the first conductive material includes copper; and providing the layer of graphene includes depositing the graphene on the copper.

18 . The method of claim 15 , wherein:
providing the second conductive material includes selectively depositing the second conductive material over the graphene and not over the insulator material.

19 . The method of claim 18 , wherein:
the preliminary IC structure includes a liner on sidewalls of the opening; and providing the second conductive material further includes depositing the second conductive material over the liner.

20 . The method of claim 15 , wherein:
providing the layer of graphene includes providing a monolayer of graphene having a thickness in a range of 8-12 Angstrom; and providing the second conductive material includes providing a layer of the second conductive material having a thickness in a range of 1.7-2 nanometers.

Assignees

• Intel Corp

Inventors

• Esan Dominic
• Kumar Kitty
• Sims Patrick
• Dassanayake Arosha
• Walker Bryce
• Ghadge Shrinath
• Su Qing
• Al-Kukhun Ahmad

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/037 Primary

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title