Fin field-effect transistor device and method

Patent metadata

Field	Value
Publication number	US-2025338613-A1
Application number	US-202519263290-A
Country	US
Kind code	A1
Filing date	Jul 8, 2025
Priority date	Mar 30, 2021
Publication date	Oct 30, 2025
Grant date	—

Abstract

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a fin protruding above the substrate; a gate structure over the fin; a first interlayer dielectric (ILD) layer over the fin and around the gate structure; a first air gap in the first ILD layer adjacent to the fin, wherein a longitudinal axis of the first air gap extends parallel to a longitudinal axis of the fin; and a dielectric layer over the first ILD layer, wherein the dielectric layer seals the first air gap to form a first enclosed cavity.

2 . The semiconductor device of claim 1 , further comprising a dummy contact plug that extends through the dielectric layer and into the first enclosed cavity.

3 . The semiconductor device of claim 2 , further comprising a liner material along sidewalls and a bottom of the dummy contact plug, wherein the liner material along the sidewalls of the dummy contact plug is spaced apart from the first ILD layer.

4 . The semiconductor device of claim 3 , further comprising isolation regions on opposing sides of the fin, wherein the first air gap extends through the first ILD layer and exposes a portion of the isolation regions.

5 . The semiconductor device of claim 4 , wherein the liner material along the bottom of the dummy contact plug extends into the portion of the isolation regions.

6 . The semiconductor device of claim 3 , further comprising a second ILD layer over the first ILD layer, wherein a first portion of the second ILD layer is between the first ILD layer and the dielectric layer, and a second portion of the second ILD layer is between the dielectric layer and the first air gap, wherein the liner material along the sidewalls of the dummy contact plug is spaced apart from the second ILD layer.

7 . The semiconductor device of claim 6 , wherein a dielectric constant of the dielectric layer is smaller than that of the first ILD layer and that of the second ILD layer.

8 . The semiconductor device of claim 6 , wherein an upper surface of the dummy contact plug is level with an upper surface of the second ILD layer distal from the substrate.

9 . The semiconductor device of claim 1 , further comprising:
a source/drain region over the fin adjacent to the gate structure; a source/drain contact plug over and electrically coupled to the source/drain region, wherein the source/drain contact plug extends into the first ILD layer; and a second air gap in the first ILD layer and around the source/drain contact plug, wherein the dielectric layer seals the second air gap to form a second enclosed cavity.

10 . The semiconductor device of claim 9 , further comprising a liner material around the source/drain contact plug, wherein the liner material is spaced apart from the first ILD layer.

11 . A semiconductor device comprising:
a channel region above a substrate; a gate structure over the channel region; a source/drain region adjacent to the gate structure; a first interlayer dielectric (ILD) layer over the source/drain region and around the gate structure; a source/drain contact in the first ILD layer and electrically coupled to the source/drain region; and a first air gap in the first ILD layer around the source/drain contact, wherein the first air gap separates the source/drain contact from the first ILD layer.

12 . The semiconductor device of claim 11 , further comprising a conductive liner material along sidewalls of the source/drain contact and along a bottom surface of the source/drain contact facing the source/drain region, wherein exterior sidewalls of the conductive liner material facing away from the source/drain contact are exposed to the first air gap.

13 . The semiconductor device of claim 12 , further comprising:
a second air gap in the first ILD layer and adjacent to the channel region, wherein a longitudinal axis of the second air gap is parallel to a longitudinal axis of the channel region; and a dielectric layer over the first ILD layer, wherein the dielectric layer seals the first air gap and the second air gap to form a first enclosed cavity and a second enclosed cavity, respectively.

14 . The semiconductor device of claim 13 , further comprising a dummy via extending into the second enclosed cavity, wherein the conductive liner material extends along sidewalls of the dummy via and along a bottom surface of the dummy via facing the substrate, wherein exterior sidewalls of the conductive liner material facing away from the dummy via are exposed to the second air gap.

15 . The semiconductor device of claim 14 , further comprising a second ILD layer between the first ILD layer and the dielectric layer, wherein the source/drain contact and the dummy via extend through the second ILD layer, wherein a first upper surface of the source/drain contact and a second upper surface of the dummy via are level with an upper surface of the second ILD layer distal from the substrate.

16 . The semiconductor device of claim 13 , wherein a dielectric constant of the dielectric layer is smaller than that of the first ILD layer.

17 . A semiconductor device comprising:
a substrate; a first fin and a second fin that protrude above the substrate; a gate structure over the first fin and the second fin; a source/drain region over the first fin and adjacent to the gate structure; a first interlayer dielectric (ILD) layer over the first fin, over the second fin, over the source/drain region, and around the gate structure; a first air gap in the first ILD layer between the first fin and the second fin; a dummy via extending through the first ILD layer and into the first air gap, wherein the dummy via is spaced apart from the first ILD layer by the first air gap; a via over and electrically coupled to the source/drain region; and a second air gap in the first ILD layer and around the via, wherein the via is spaced apart from the first ILD layer by the second air gap.

18 . The semiconductor device of claim 17 , further comprising a second ILD layer over the first ILD layer and the first air gap, wherein an upper surface of the dummy via and an upper surface of the via are level with an upper surface of the second ILD layer distal from the substrate.

19 . The semiconductor device of claim 18 , further comprising a dielectric layer over the second ILD layer, wherein the dielectric layer seals the first air gap and the second air gap to form a first enclosed cavity and a second enclosed cavity, respectively.

20 . The semiconductor device of claim 18 , further comprising an isolation region between the first fin and the second fin, wherein the first air gap is between the isolation region and the second ILD layer, wherein the first air gap has a protrusion that extends into the isolation region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Chui Chi On

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10D84/0158 Primary

  the components including FinFETs · CPC title