Via bars interleaved with capacitor structure

Patent metadata

Field	Value
Publication number	US-2025329631-A1
Application number	US-202418639641-A
Country	US
Kind code	A1
Filing date	Apr 18, 2024
Priority date	Apr 18, 2024
Publication date	Oct 23, 2025
Grant date	—

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to via bars interleaved between conductive plates of a capacitor structure and methods of manufacture. The structure includes: a capacitor structure having a plurality of capacitor plates within layers of dielectric material; a wiring structure in a lower layer of the dielectric material, the wiring structure electrically connecting to one of the capacitor plates; and a plurality of via bars within the layers of dielectric material and interleaved with the plurality of capacitor plates. The plurality of via bars have a different width dimension than the plurality of capacitor plates.

First claim

What is claimed:

1 . A structure comprising:
a capacitor structure comprising a plurality of capacitor plates within layers of dielectric material; a wiring structure in a lower layer of the dielectric material, the wiring structure electrically connecting to one of the capacitor plates; and a plurality of via bars within the layers of dielectric material and interleaved with the plurality of capacitor plates, the plurality of via bars comprising a different width dimension than the plurality of capacitor plates.

2 . The structure of claim 1 , wherein the capacitor plates comprise a comb structure.

3 . The structure of claim 2 , wherein the plurality of via bars comprise a comb structure interleaved within the capacitor plates.

4 . The structure of claim 2 , wherein the via bars connect to an underlying metal wiring layer in the lower layer of the dielectric material.

5 . The structure of claim 1 , wherein the plurality of capacitor plates are interleaved with one another.

6 . The structure of claim 5 , wherein the plurality of interleaved capacitor plates comprise a first comb structure interleaved with a second comb structure.

7 . The structure of claim 6 , wherein the first comb structure is a top comb structure and the second comb structure is a bottom comb structure.

8 . The structure of claim 6 , wherein the plurality of via bars are free floating via bars.

9 . The structure of claim 8 , wherein the free floating via bars are between the plurality of capacitor plates of the first comb structure and the second comb structure.

10 . The structure of claim 1 , wherein the plurality of via bars do not overlap with the plurality of capacitor plates.

11 . The structure of claim 1 , wherein the plurality of via bars have a smaller width dimension than the plurality of the capacitor plates.

12 . The structure of claim 1 , wherein a spacing between each of the plurality of via bars and adjacent capacitor plates of the plurality of capacitor plates is less than the width dimension of the plurality of via bars.

13 . A structure comprising:
a plurality of capacitor plates; a wiring structure electrically connecting to one of the capacitor plates; and a plurality of via bars interleaved with the plurality of capacitor plates, the plurality of via bars comprising a smaller width dimension than the plurality of capacitor plates.

14 . The structure of claim 13 , wherein the capacitor plates comprise a comb structure.

15 . The structure of claim 13 , wherein the plurality of via bars comprise a comb structure interleaved within the capacitor plates.

16 . The structure of claim 13 , wherein the via bars connect to an underlying metal wiring layer in dielectric material.

17 . The structure of claim 13 , wherein the plurality of interleaved capacitor plates comprise a first comb structure interleaved with a second comb structure and the via bars are free floating between the interleaved capacitor plates of the first comb structure and the second comb structure.

18 . The structure of claim 13 , wherein the plurality of via bars do not overlap with the plurality of capacitor plates.

19 . The structure of claim 13 , wherein a spacing between each of the plurality of via bars and adjacent capacitor plates of the plurality of capacitor plates is less than a width between the adjacent capacitor plates.

20 . A method comprising:
forming a capacitor structure comprising a plurality of capacitor plates within layers of dielectric material; forming a wiring structure in a lower layer of the dielectric material, the wiring structure electrically connecting to one of the capacitor plates; and forming a plurality of via bars within the layers of dielectric material and interleaved with the plurality of capacitor plates, the plurality of via bars comprising a different width dimension than the plurality of capacitor plates.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• KHOR Ee Jan
• Yi Wanbing

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H01G13/00

  Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00 · CPC title

• H01G4/002

  Details · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title