Self-aligned contact air gap formation

US2025324683A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025324683-A1
Application numberUS-202519247644-A
CountryUS
Kind codeA1
Filing dateJun 24, 2025
Priority dateSep 27, 2018
Publication dateOct 16, 2025
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

First claim

Opening claim text (preview).

What is claimed is: 1 . A device structure, comprising: an active region comprising a first channel region, a second channel region and a source/drain region between the first channel region and the second channel region along a direction; a first gate stack over the first channel region; a first gate spacer extending along a sidewall of the first gate stack; a second gate stack over the second channel region; a second gate spacer extending along a sidewall of the second gate stack; a source/drain feature disposed in the source/drain region; and a contact plug over the source/drain feature and disposed between the first gate stack and the second gate stack, wherein the contact plug is spaced apart from the sidewall of the first gate stack by a first air gap and the first gate spacer, wherein the contact plug is spaced apart from the sidewall of the second gate stack by a second air gap, an interlayer dielectric layer, a contact etch stop layer, and the second gate spacer. 2 . The device structure of claim 1 , wherein the first air gap laterally extends over a top surface of the first gate stack, wherein the second air gap does not laterally extend over a top surface of the second gate stack. 3 . The device structure of claim 1 , further comprising: an interlayer dielectric (ILD) layer over the first gate stack and the second gate stack; and a seal layer over the ILD layer and the contact plug. 4 . The device structure of claim 3 , wherein the seal layer is disposed over the first air gap and the second air gap to seal them. 5 . The device structure of claim 3 , wherein the seal layer partially extends between the ILD layer and the contact plug. 6 . The device structure of claim 1 , wherein the first gate spacer comprises a rounded corner profile. 7 . The device structure of claim 1 , further comprising: a nitride liner disposed along sidewalls of the contact plug. 8 . The device structure of claim 7 , wherein the nitride liner comprises carbon-doped silicon nitride. 9 . The device structure of claim 1 , further comprising: a metal silicide layer disposed between the contact plug and the source/drain feature, wherein the metal silicide layer comprises nickel silicide, cobalt silicide, or titanium silicide. 10 . A structure, comprising: a first gate stack and a second gate stack; a contact plug disposed between the first gate stack and the second gate stack along a direction; a first gate spacer disposed along a sidewall of the first gate stack; a second gate spacer disposed along a sidewall of the second gate stack; a contact etch stop layer (CESL) having a first portion disposed over the first gate stack and a second portion disposed over the second gate stack; an interlayer dielectric (ILD) layer having a first portion over the first portion of the CESL and a second portion over the second portion of the CESL; a first air gap disposed between the contact plug and the first gate stack; a second air gap disposed between the contact plug and the second gate stack; and a seal layer over the ILD layer, the first air gap, the contact plug, and the second air gap, wherein the contact plug is closer to the first gate spacer than to the second gate spacer. 11 . The structure of claim 10 , wherein the first gate stack and the first gate spacer are exposed in the first air gap. 12 . The structure of claim 10 , wherein the second gate stack and the second gate spacer are not exposed in the second air gap. 13 . The structure of claim 10 , wherein the first air gap laterally extends over a top surface of the first gate stack, wherein the second air gap does not laterally extend over a top surface of the second gate stack. 14 . The structure of claim 10 , wherein the first gate spacer comprises a rounded corner profile. 15 . The structure of claim 10 , further comprising: a nitride liner disposed along sidewalls of the contact plug such that the nitride liner is disposed between the first air gap and the contact plug along the direction and is disposed between the second air gap and the contact plug along the direction. 16 . The structure of claim 15 , wherein the nitride liner comprises carbon-doped silicon nitride. 17 . A device structure, comprising: an active region comprising a first channel region, a second channel region and a source/drain region between the first channel region and the second channel region along a direction; a first gate stack over the first channel region; a second gate stack over the second channel region; a source/drain feature over the source/drain region; a contact plug disposed over the source/drain feature;; a first gate spacer disposed along a sidewall of the first gate stack; a second gate spacer disposed along a sidewall of the second gate stack; a contact etch stop layer (CESL) having a first portion disposed over the first gate stack and a second portion disposed over the second gate stack and the second gate spacer; an interlayer dielectric (ILD) layer having a first portion over the first portion of the CESL and a second portion over the second portion of the CESL; a first air gap disposed between the contact plug and the first gate stack; a second air gap disposed between the contact plug and the second gate stack; and a seal layer over the ILD layer, the first air gap, the contact plug, and the second air gap, wherein the first air gap laterally extends over a top surface of the first gate stack, wherein the second air gap does not laterally extend over a top surface of the second gate stack. 18 . The device structure of claim 17 , wherein the first gate stack and the first gate spacer are exposed in the first air gap, wherein the second gate stack and the second gate spacer are not exposed in the second air gap. 19 . The device structure of claim 17 , further comprising: a nitride liner disposed along sidewalls of the contact plug such that the nitride liner is disposed between the first air gap and the contact plug along the direction and is disposed between the second air gap and the contact plug along the direction. 20 . The device structure of claim 17 , wherein the contact plug is closer to the first gate spacer than to the second gate spacer.

Assignees

Inventors

Classifications

  • Seals · CPC title

  • of dielectric parts comprising air gaps · CPC title

  • H10W20/069Primary

    by forming self-aligned vias or self-aligned contact plugs · CPC title

  • comprising air gaps · CPC title

  • of conductive barrier, adhesion or liner layers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2025324683A1 cover?
In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 16 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).