Scalable patterning through layer expansion process and resulting structures

Patent metadata

Field	Value
Publication number	US-2025323092-A1
Application number	US-202519247647-A
Country	US
Kind code	A1
Filing date	Jun 24, 2025
Priority date	Mar 30, 2021
Publication date	Oct 16, 2025
Grant date	—

Abstract

Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer over a substrate having multiple structures formed therein; forming a single opening in the dielectric layer, the single opening exposing one or more of the multiple structures; forming a mask layer over the dielectric layer, wherein the mask layer includes openings that expose selected portions of the dielectric layer around a perimeter of the single opening while covering other portions of the dielectric layer; implanting dopant species through the openings in the mask layer into the selected portions of the dielectric layer to cause the selected portions to expand laterally into the single opening; and wherein the expansion of the selected portions divides the single opening into multiple separate sub-openings, each sub-opening aligned with one of the multiple structures.

2 . The method of claim 1 , wherein the multiple structures comprise at least one of gate electrodes, source regions, and drain regions.

3 . The method of claim 1 , wherein the dopant species comprises a dopant selected from the group consisting of germanium, argon, xenon, and silicon, and combinations thereof, and wherein the dopant species has an atomic radius at least as great as silicon.

4 . The method of claim 1 , wherein implanting the dopant species comprises implanting with an energy in a range from about 0.5K eV to about 50K eV per dose and a resulting dopant concentration of from about 10 19 to about 10 22 atoms/cm 3 .

5 . The method of claim 1 , wherein forming the mask layer comprises depositing at least one of a photoresist material, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer, and patterning the deposited material to form the openings in the mask layer.

6 . The method of claim 1 , further comprising filling the multiple separate sub-openings with conductive material to form multiple conductive vias, each conductive via electrically contacting a respective one of the multiple structures.

7 . The method of claim 1 , wherein the expansion of the selected portions causes the dielectric layer to expand by about 3% to about 7% in regions where the dopant species is implanted.

8 . A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer over a substrate having a structure formed therein; forming an opening in the dielectric layer to expose the structure, the opening having an initial width; implanting a dopant species into the dielectric layer with a concentration gradient that decreases from a top surface of the dielectric layer toward a bottom surface of the dielectric layer; wherein the implanting causes greater expansion of the dielectric layer at the top surface than at the bottom surface, resulting in the opening having a tapered profile with a width that increases from the top surface toward the bottom surface; and filling the opening having the tapered profile with conductive material to form a conductive via.

9 . The method of claim 8 , wherein the structure comprises a gate electrode, a source region, or a drain region.

10 . The method of claim 8 , wherein the dopant species comprises a material selected from the group consisting of germanium, argon, xenon, and silicon, and combinations thereof, the dopant species having an atomic radius at least as great as silicon.

11 . The method of claim 8 , wherein implanting the dopant species comprises performing the implantation at an energy in a range from about 0.5K eV to about 50K eV per dose and a dose ranging between about 10 13 and 10 16 atoms/cm 2 .

12 . The method of claim 8 , wherein implanting the dopant species causes the dielectric layer to expand by about 3% to about 7% at the top surface of the dielectric layer.

13 . The method of claim 8 , wherein implanting the dopant species comprises implanting at a tilt angle between 0 degrees and 60 degrees relative to a vertical axis and at a temperature between about −100° C. and about 450° C.

14 . The method of claim 8 , wherein the dielectric layer comprises a material selected from the group consisting of tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), and boron doped silicon glass (BSG).

15 . A method of manufacturing a semiconductor device, comprising:
forming multiple structures in a substrate; forming a dielectric layer over the multiple structures; patterning the dielectric layer to form a single opening that exposes at least one of the multiple structures; applying a multi-step implantation process to the dielectric layer, wherein each step of the multi-step implantation process uses one or more of a different implantation energy, implantation dosage, or implantation angle; wherein the multi-step implantation process causes selected portions of the dielectric layer to expand laterally into the single opening, dividing the single opening into multiple separate sub-openings; and filling the multiple separate sub-openings with conductive material to form multiple separate conductive vias, each conductive via contacting a respective one of the multiple structures.

16 . The method of claim 15 , wherein the multiple structures comprise one or more gate electrodes, source regions, or drain regions.

17 . The method of claim 15 , wherein the multi-step implantation process comprises implanting a dopant species having an atomic radius at least as great as silicon, wherein the dopant species comprises a material selected from the group consisting of germanium, argon, xenon, and silicon, and combinations thereof.

18 . The method of claim 15 , wherein at least one step of the multi-step implantation process comprises implanting at an energy in a range from about 0.5K eV to about 50K eV per dose and a dose ranging between about 10 13 and 10 16 atoms/cm 2 .

19 . The method of claim 15 , wherein the dielectric layer comprises a material selected from the group consisting of tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), and boron doped silicon glass (BSG).

20 . The method of claim 15 , wherein the lateral expansion of the selected portions of the dielectric layer causes the selected portions to expand by about 3% to about 7%.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Chui Chi On

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/095 Primary

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/082 Primary

  the openings being tapered via holes · CPC title