Semiconductor device having a uniform and thin silicide layer on an epitaxial source/drain structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025323043-A1
Application number	US-202519248971-A
Country	US
Kind code	A1
Filing date	Jun 25, 2025
Priority date	Jan 14, 2016
Publication date	Oct 16, 2025
Grant date	—

Abstract

In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
performing a conformal deposition process to deposit an amorphous layer over an epitaxial semiconductor layer; depositing a metal second layer over the amorphous layer; depositing a third layer comprising a transition metal nitride over the metal second layer; performing a thermal process, thereby forming an alloy layer of the amorphous layer and the metal second layer; and after performing the thermal process, removing the third layer, thereby exposing a surface of the alloy layer.

2 . The method of claim 1 , further comprising:
after removing the third layer, forming an insulating layer in direct contact with the surface of the alloy layer.

3 . The method of claim 1 , wherein the amorphous layer comprises amorphous silicon or amorphous germanium.

4 . The method of claim 1 , wherein:
the amorphous layer comprises amorphous silicon; and the metal second layer is at least one of Ti, Co, Ni, W, or Ta.

5 . The method of claim 1 , wherein:
the amorphous layer comprises amorphous silicon, the metal second layer comprises Ti, and the third layer comprises TiN.

6 . The method of claim 1 , wherein the thermal process is performed at a temperature of 500° C. to 1000° C.

7 . The method of claim 1 , wherein the thermal process is performed for a time duration of between 1 usec and 1 msec.

8 . The method of claim 1 , wherein a thickness of the amorphous layer is in a range from 1 nm to 10 nm.

9 . The method of claim 1 , wherein the alloy layer has a substantially uniform thickness with a thickness variation that is not greater than ±1.0 nm.

10 . The method of claim 1 , wherein by the thermal process, the amorphous layer is fully consumed in forming the alloy layer.

11 . The method of claim 1 , further comprising:
performing a cleaning process before depositing the metal second layer.

12 . A semiconductor device, comprising:
a substrate; a fin structure formed over the substrate; a source/drain epitaxial layer formed over the fin structure; a silicide layer, comprising least one of Ti, Co, Ni, W, or Ta, formed on a surface of the source/drain epitaxial layer; and a source/drain contact disposed on the silicide layer, wherein a bottommost portion of the source/drain contact, which is closest to the substrate along a direction normal to an upper surface of the substrate is located closer to the substrate than a bottommost portion of the silicide layer, which is closest to the substrate along the direction normal to the upper surface of the substrate.

13 . The semiconductor device of claim 12 , wherein the silicide layer has a substantially uniform thickness that is in a range from 1 nm to 10 nm.

14 . The semiconductor device of claim 12 , wherein the silicide layer includes TiSi.

15 . The semiconductor device of claim 12 , wherein the source/drain contact covers the silicide layer.

16 . The semiconductor device of claim 15 , wherein the source/drain contact includes a first layer comprising TiN or TaN and a second layer comprising Co.

17 . A semiconductor device comprising:
a substrate; a fin structure disposed over the substrate; a source/drain epitaxial layer formed on an upper portion of the fin structure; and a source/drain contact, wherein:
an upper portion of the source/drain epitaxial layer has a rhombus shape including a top, a first side corner and a second side corner both located below the top;
a silicide layer, comprising least one of Ti, Co, Ni, W, or Ta, is formed on the upper portion of the source/drain epitaxial layer covering the top, the first side corner and a part of the upper portion of the source/drain epitaxial layer between the top and the second side corner, and
the source/drain contact is in contact with the silicide layer disposed on the first side corner, and the second side corner is covered by an insulating layer in direct contact with the second side corner.

18 . The semiconductor device of claim 17 , wherein the source/drain contact includes a Co layer.

19 . The semiconductor device of claim 17 , wherein the silicide layer includes TiSi.

20 . The semiconductor device of claim 17 , wherein a fin liner layer is disposed on a lower portion of the source/drain epitaxial layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Sheu Jyh-Cherng
• Wang Sung-Li
• Yang Cheng-Yu
• Wang Sheng-Chen
• Yeong Sai-Hooi

Classifications

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/066

  by forming silicides of refractory metals · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title