Methods to improve magnetic tunnel junction memory cells by treating native oxide

Patent metadata

Field	Value
Publication number	US-2025318436-A1
Application number	US-202519242387-A
Country	US
Kind code	A1
Filing date	Jun 18, 2025
Priority date	Oct 31, 2018
Publication date	Oct 9, 2025
Grant date	—

Abstract

Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a dielectric stack over an interconnect structure, the dielectric stack comprising:
a first metal nitride layer over the interconnect structure, the first metal nitride layer comprising a first metal;
a metal oxide layer over the first metal nitride layer, the metal oxide layer comprising the first metal;
a silicon oxide layer over the metal oxide layer; and
an anti-reflective coating over the silicon oxide layer;
a bottom electrode via embedded in the dielectric stack; a bottom electrode over the bottom electrode via; a metal tunnel junction (MTJ) layer over the bottom electrode; a top electrode over the MTJ layer, the top electrode comprising:
a second metal nitride layer over the MTJ layer, the second metal nitride layer comprising a first material, the second metal nitride layer comprising a second metal;
a metal layer over the second metal nitride layer, the metal layer comprising a second material different from the first material, the metal layer comprising a third metal; and
a third metal nitride layer over the metal layer, the third metal nitride layer comprising a third material different from the first material and the second material, the third metal nitride layer comprising the third metal;
a dielectric spacer over the dielectric stack and along a sidewall of the bottom electrode, a sidewall of the MTJ layer, and a sidewall of the top electrode; and a protective layer over the dielectric spacer and along the sidewall of the top electrode.

2 . The semiconductor device of claim 1 , wherein a metal of the first metal nitride layer is the same as a metal of the metal oxide layer.

3 . The semiconductor device of claim 1 , wherein the dielectric spacer is in contact with the sidewall of the top electrode.

4 . The semiconductor device of claim 3 , wherein the protective layer is in contact with the sidewall of the top electrode.

5 . The semiconductor device of claim 4 , wherein the dielectric spacer and the protective layer are in contact with the metal layer of the top electrode.

6 . The semiconductor device of claim 1 , further comprising:
a dielectric fill material over the protective layer; and an additional interconnect structure over the top electrode and the dielectric fill material, wherein the additional interconnect structure comprises metallization layers embedded in an insulating film.

7 . The semiconductor device of claim 6 , wherein the insulating film physically contacts the dielectric fill material, the protective layer, and the third metal nitride layer.

8 . A semiconductor device comprising:
a plurality of dielectric layers disposed over a substrate; a bottom electrode via embedded in the plurality of dielectric layers; a magnetic random access memory (MRAM) cell disposed over the bottom electrode via, the MRAM cell comprising:
a bottom electrode layer disposed over the bottom electrode via;
a magnetic tunnel junction (MTJ) layer disposed over the bottom electrode layer; and
a top electrode layer disposed over the MTJ layer;
a dielectric spacer disposed around and physically contacting a sidewall of a first layer of the plurality of dielectric layers, a sidewall and an upper surface of a second layer of the plurality of dielectric layers, and a sidewall of the MRAM cell, the dielectric spacer having a first lateral thickness adjacent to the plurality of dielectric layers, the dielectric spacer having a second lateral thickness adjacent to the MTJ layer, the first lateral thickness being greater than the second lateral thickness; and a protective layer disposed over and physically contacting the dielectric spacer and physically contacting the sidewall of the MRAM cell.

9 . The semiconductor device of claim 8 , wherein a third lateral thickness of the protective layer adjacent to the MRAM cell is greater than the second lateral thickness of the dielectric spacer.

10 . The semiconductor device of claim 8 , wherein the first layer of the plurality of dielectric layers comprises an anti-reflective coating, and wherein the second layer of the plurality of dielectric layers comprises tetraethyl orthosilicate.

11 . The semiconductor device of claim 10 , wherein the anti-reflective coating is a nitrogen-free reflective coating.

12 . The semiconductor device of claim 8 , wherein the sidewall of the MRAM cell is level with the sidewall of the second layer of the plurality of dielectric layers.

13 . The semiconductor device of claim 8 , wherein the top electrode layer comprises:
a first metal nitride layer disposed over the MTJ layer; one or more conductive layers disposed over the first metal nitride layer; and a second metal nitride layer disposed over the one or more conductive layers.

14 . The semiconductor device of claim 13 , wherein the dielectric spacer physically contacts the first metal nitride layer and the one or more conductive layers, and wherein the protective layer physically contacts the second metal nitride layer and the one or more conductive layers.

15 . A semiconductor device comprising:
a dielectric stack disposed over a first interconnect structure, the dielectric stack comprising a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer; a bottom electrode via extending through an entirety of the dielectric stack and disposed over the first interconnect structure; a bottom electrode over the bottom electrode via; a magnetic tunnel junction (MTJ) layer over the bottom electrode; a top electrode over the MTJ, sidewalls of the top electrode, the MTJ layer, the bottom electrode, and the third dielectric layer being level with one another; a spacer over and physically contacting the second dielectric layer, the third dielectric layer, and the sidewalls of the top electrode, the MTJ layer, and the bottom electrode; a dielectric cover layer disposed over the spacer and physically contacting the second dielectric layer and the sidewall of the top electrode; and a second interconnect structure over the top electrode.

16 . The semiconductor device of claim 15 , wherein the bottom electrode comprises:
a first tantalum nitride layer; and a first titanium nitride layer over the first tantalum nitride layer.

17 . The semiconductor device of claim 16 , wherein the top electrode comprises:
a second titanium nitride layer over the MTJ layer; a metal alloy layer over the second titanium nitride layer; and a second tantalum nitride layer.

18 . The semiconductor device of claim 15 , wherein the second dielectric layer comprises an L-shape, and wherein sidewalls of the second dielectric layer and the third dielectric layer are level with the sidewalls of the bottom electrode, the MTJ layer, and the top electrode.

19 . The semiconductor device of claim 15 , further comprising a dielectric fill material around the dielectric cover layer, wherein upper surfaces of the dielectric fill material, the dielectric cover layer, and the top electrode are level with one another.

20 . The semiconductor device of claim 15 , wherein the MTJ layer comprises:
a conductive alloy layer over the bottom electrode; a metal oxide layer over the conductive alloy layer; and a dielectric alloy layer over the metal oxide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Jung-Tang
• Wu meng yu
• Wu Szu-Hua
• Lee Chin-Szu

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title