Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025318130-A1
Application number	US-202519246893-A
Country	US
Kind code	A1
Filing date	Jun 24, 2025
Priority date	Sep 25, 2020
Publication date	Oct 9, 2025
Grant date	—

Abstract

The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers alternately stacked with a plurality of gate electrodes on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a first region of the core insulating layer is lower than a dielectric constant of a second region of the core insulating layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a stack including a plurality of interlayer insulating layers alternately stacked with a plurality of gate electrodes on a substrate; and a plurality of channel structures passing through the stack in a vertical direction; wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures; wherein a dielectric constant of a first region of the core insulating layer, which corresponds to a source select transistor or a drain select transistor, is lower than a dielectric constant of a second region of the core insulating layer that corresponds to memory cells; and wherein the first region of the core insulating layer includes a gap.

2 . The semiconductor memory device of claim 1 , wherein at least one first gate electrode disposed at an uppermost portion of the plurality of gate electrodes corresponds to a first select transistor, and at least one second gate electrode disposed at a lowermost portion of the plurality of gate electrodes corresponds to a second select transistor.

3 . The semiconductor memory device of claim 2 , wherein the first region of the core insulating layer is adjacent to the first gate electrode or the second gate electrode.

4 . A semiconductor memory device comprising:
a stack including a plurality of interlayer insulating layers alternately stacked with a plurality of gate electrodes on a substrate; and a plurality of channel structures passing through the stack in a vertical direction; wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures; at least one first gate electrode disposed at an uppermost portion of the plurality of gate electrodes corresponds to a drain select transistor, at least one second gate electrode disposed at a lowermost portion of the gate electrodes corresponds to a source select transistor, and at least one third gate electrode, excluding the at least one first gate electrode and at least one second gate electrode among the plurality of gate electrodes, corresponding to the memory cells; and a first region of the core insulating layer adjacent to the first gate electrode or the second gate electrode has a dielectric constant lower than a dielectric constant of a second region adjacent to the at least one third gate electrode; wherein a gap is formed in the first region of the core insulating layer.

Assignees

• Sk Hynix Inc

Inventors

• Yun dae hwan
• Choi Gil Bok

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title