Continuous-time delta-sigma analog-to-digital converter with duty-cycle-controlled input path

Patent metadata

Field	Value
Publication number	US-2025317152-A1
Application number	US-202418630959-A
Country	US
Kind code	A1
Filing date	Apr 9, 2024
Priority date	Apr 9, 2024
Publication date	Oct 9, 2025
Grant date	—

Abstract

A delta-sigma analog-to-digital converter is provided that includes a continuous-time integration stage having an input terminal coupled through a switch to an input resistor that in turn couples to an input signal node. A feedback digital-to-analog converter converts a digital output signal to form a feedback current that also couples to the input terminal. A controller switches the first switch responsive to a duty cycle of the feedback current.

First claim

What is claimed is:

1 . A continuous-time delta-sigma analog-to-digital converter, comprising:
an input signal node for an analog input signal; a continuous-time integration stage including a first input terminal; an input resistor coupled to the input signal node; a first switch coupled between the input resistor and the first input terminal; a return-to-zero digital-to-analog converter configured to pulse a feedback current to the first input terminal; and a controller configured to switch the first switch responsive to an integration pulse width of the feedback current.

2 . The continuous-time delta-sigma analog-to-digital converter of claim 1 , wherein the controller is configured to switch on the first switch during the integration pulse width and to switch off the first switch during an off time of the feedback current.

3 . The continuous-time delta-sigma analog-to-digital converter of claim 1 , wherein the continuous-time integration stage includes an operational transconductance amplifier having the first input terminal and having a second input terminal coupled to ground.

4 . The continuous-time delta-sigma analog-to-digital converter of claim 3 , wherein the first input terminal is an inverting input terminal and the second input terminal is a non-inverting input terminal.

5 . The continuous-time delta-sigma analog-to-digital converter of claim 3 , wherein the continuous-time integration stage includes a capacitor coupled between the first input terminal and an output terminal of the operational transconductance amplifier.

6 . The continuous-time delta-sigma analog-to-digital converter of claim 1 , further comprising:
a quantizer configured to quantize an integrated output signal from the continuous-time integration stage to form a digital output signal, wherein the return-to-zero digital-to-analog converter is configured to convert the digital output signal to form the feedback current.

7 . The continuous-time delta-sigma analog-to-digital converter of claim 2 , further comprising:
a second switch coupled between the first input terminal and ground.

8 . The continuous-time delta-sigma analog-to-digital converter of claim 7 , wherein the controller is further configured to switch off the second switch during the integration pulse width and to switch on the second switch during the off time of the feedback current.

9 . The continuous-time delta-sigma analog-to-digital converter of claim 6 , wherein the quantizer is a successive-approximation-register quantizer, and wherein the continuous-time delta-sigma analog-to-digital converter is included within a cellular telephone.

10 . A continuous-time delta-sigma analog-to-digital converter, comprising:
an input signal node for an analog input signal; a continuous-time integration stage including a first input terminal; an input resistor coupled to the input signal node; a first switch coupled between the input resistor and the first input terminal; a capacitive digital-to-analog converter configured to transiently pulse a feedback current to the first input terminal during an integration pulse width of a clock signal; and a controller configured to switch the first switch on during an off time of the clock signal and to switch the first switch off during the integration pulse width.

11 . The continuous-time delta-sigma analog-to-digital converter of claim 10 , wherein the continuous-time integration stage includes an operational transconductance amplifier having the first input terminal and having a second input terminal coupled to ground.

12 . The continuous-time delta-sigma analog-to-digital converter of claim 11 , wherein the first input terminal is an inverting input terminal and the second input terminal is a non-inverting input terminal.

13 . The continuous-time delta-sigma analog-to-digital converter of claim 11 , wherein the continuous-time integration stage includes a capacitor coupled between the first input terminal and an output terminal of the operational transconductance amplifier.

14 . The continuous-time delta-sigma analog-to-digital converter of claim 10 , further comprising:
a quantizer configured to quantize an integrated output signal from the continuous-time integration stage to form a digital output signal, wherein the capacitive digital-to-analog converter is configured to convert the digital output signal to form the feedback current.

15 . The continuous-time delta-sigma analog-to-digital converter of claim 14 , wherein the quantizer is a successive-approximation-register quantizer.

16 . The continuous-time delta-sigma analog-to-digital converter of claim 10 , further comprising:
a second switch coupled between the first input terminal and ground.

17 . The continuous-time delta-sigma analog-to-digital converter of claim 16 , wherein the controller is further configured to switch on the second switch during the off time and to switch on the second switch during the integration pulse width.

18 . A method of digitizing an input current, comprising:
gating an input current responsive to a duty cycle of a clock signal to form a gated input current; integrating a difference between the gated input current and a feedback current to form an integrated output signal; quantizing the integrated output signal to form a digital output signal; and converting the digital output signal in a digital-to-analog converter responsive to the clock signal to form the feedback current.

19 . The method of claim 18 , wherein gating the input current comprises switching off an input switch for the input current during an off time of the clock cycle and switching on the input switch during an integration pulse width of the clock cycle, and wherein converting the digital output signal in the digital-to-analog converter comprises converting the digital output signal in a return-to-zero digital-to-analog converter.

20 . The method of claim 18 , wherein gating the input current comprises switching on an input switch for the input current during an off time of the clock cycle and switching off the input switch during an integration pulse width of the clock cycle, and wherein converting the digital output signal in the digital-to-analog converter comprises converting the digital output signal in a capacitive digital-to-analog converter.

Assignees

• Qualcomm Inc

Inventors

• Hsieh Chieh-Yu
• Guo Yuhua
• Alladi Dinesh Jagannath

Classifications

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/49 Primary

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title