Programmable chopping architecture to reduce offset in an analog front end

Patent metadata

Field	Value
Publication number	US-11770109-B2
Application number	US-202217901654-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Jun 26, 2020
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

First claim

What is claimed is:

1. An analog front-end (AFE) of an analog-to-digital converter (ADC), the AFE comprising:
an amplifier coupled to receive an analog input signal;
a programmable anti-aliasing filter (AAF) coupled to an output of the amplifier;
a modulator to generate a digital data stream in response to the analog input signal;
one or more chopping circuits, wherein the programmable AAF comprises:
a first path between the amplifier and the modulator with an input resistance; and
a second path between the amplifier and the modulator that bypasses the input resistance.

2. The AFE of claim 1 , further comprising:
a control circuit to control the programmable AAF to select either the first path or the second path.

3. The AFE of claim 1 , wherein:
the first path of the programmable AAF comprises:
a first resistor coupled in series on a first line between a first output of the amplifier and a first input of the modulator;
a second resistor coupled in series on a second line between a second output of the amplifier and a second input of the modulator;
a capacitor couple between the first line and the second line; and

the second path of the programmable AAF comprises a third line coupled to a first switch and a fourth line coupled to a second switch, the first switch and the second switch to bypass the first line and the second line when activated.

4. The AFE of claim 3 , wherein the first path further comprises:
a third switch coupled between the first resistor and the first output of the amplifier;
a fourth switch coupled between the second resistor and the second output of the amplifier;
a fifth switch coupled between the first resistor and the first input of the modulator; and
a sixth switch coupled between the second resistor and the second input of the modulator.

5. The AFE of claim 3 , wherein the programmable AAF further comprises a third path between the amplifier and the modulator that bypasses the input resistance and the capacitor of the programmable AAF.

6. The AFE of claim 1 , further comprising a buffer circuit coupled to an output of the programmable AAF, wherein the modulator is a sigma-delta modulator configured to generate the digital data stream in response to an output of the buffer circuit, wherein the amplifier, the programmable AAF, the sigma-delta modulator, and the one or more chopping circuits are formed with a same integrated circuit substrate.

7. The AFE of claim 6 , wherein the one or more chopping circuits comprises a plurality of chopping circuits nested within one another, including:
a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and
a second pair of chopping circuits having at least the first pair of chopping circuits disposed therebetween.

8. The AFE of claim 7 , wherein:
the second pair of chopping circuits include the amplifier, the programmable AAF, and the buffer circuit disposed therebetween.

9. The AFE of claim 7 , wherein:
the plurality of chopping circuits further includes a third pair of chopping circuits having the buffer circuit disposed therebetween.

10. The AFE of claim 7 , wherein:
the programmable AAF is configured to change analog filter element configurations during chopping operations of the first pair of chopping circuits.

11. The AFE of claim 7 , further comprising:
a masking circuit configured to mask portions of the digital data stream output from the modulator during chopping operations of the first pair of chopping circuits.

12. The AFE of claim 11 , wherein the masking circuit further comprises:
a memory circuit configured to store portions of the digital data stream, and
a multiplexer coupled to selectively output the digital data stream or data values stored in the memory circuit.

13. The AFE of claim 1 , wherein the one or more chopping circuits comprises a plurality of chopping circuits nested within one another, including:
a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal,
a second pair of chopping circuits having at least the first pair of chopping circuits disposed therebetween; and
a third pair of chopping circuits disposed between the first pair of chopping circuits and having the amplifier disposed therebetween, wherein:
the first pair of chopping circuits operates at a first frequency,
the second pair of chopping circuits operates at a second frequency slower than the first frequency, and
the third pair of chopping circuits operates at a third frequency faster than the first frequency.

14. The AFE of claim 1 , further comprising:
an input multiplexer (MUX) configured to selectively connect one of a plurality of input signals to the amplifier as the analog input signal, wherein the programmable AAF is configured to change analog filter element configurations in the programmable AAF when the input MUX switches between input signals.

15. A method comprising:
receiving a first analog input signal at an input;
by operation of an amplifier, amplifying the first analog input signal;
filtering a first output of the amplifier with a programmable anti-aliasing filter (AAF), the first output corresponding to the first analog input signal;
modulating a first output of programmable AAF with a modulator into a first portion of a digital data stream;
receiving a second analog input signal at the input;
by operation of the amplifier, amplifying the second analog input signs signal;
bypassing filtering a second output of the amplifier with the programmable AAF, the second output corresponding to the second analog input signal;
modulating a second output of the programmable AAF with the modulator into a second portion of the digital data stream; and
chopping analog signals at locations between the input and the modulator with one or more chopping circuits.

16. The method of claim 15 , further comprising:
changing programmable AAF analog filter element configurations during chopping operations of the one or more chopping circuits.

17. The method of claim 15 , further comprising buffering an output of the programmable AAF with a buffer circuit, wherein chopping analog signals comprises:
chopping the first analog input signal at the input of the amplifier and the output of the buffer with a first pair of chopping circuits; and
chopping the first analog input signal at the input of the amplifier and the output of the amplifier with a second pair of chopping circuits.

18. The method of claim 17 , wherein chopping analog signals further comprises:
chopping the first analog input signal at the input of the amplifier and the first output of the amplifier with a third pair of chopping circuits nested within the second pair of chopping circuits; wherein:
the first pair of chopping circuits operates at a first frequency;
the second pair of chopping circuits operates at a second frequency faster than the first frequency; and
the third pair of chopping circuits operates at a third frequency faster than the second frequency.

19. The method of claim 15 , further comprising:
masking portions of the digital data stream output from the modulator during chopping operations of the one or more chopping circuits.

20. The method of claim 15 , further comprising:
selectively connecting the first analog input signal and the second analog input signal to the input as an analog input by operation of an input multiplexe

Assignees

• Cypress Semiconductor Corp

Inventors

• Hancioglu Erhan
• Thiagarajan Eashwar
• Mann Eric
• Kutz Harold
• Ramamoorthy Vaibhav
• Singh Rajiv
• Richardson Jr Amsby

Classifications

• H03F3/387 Primary

  with semiconductor devices only · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03F1/02

  Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation · CPC title

• H03F2200/171

  A filter circuit coupled to the output of an amplifier · CPC title

• H03F2200/331

  Sigma delta modulation being used in an amplifying circuit · CPC title