Methods of forming semiconductor packages

Patent metadata

Field	Value
Publication number	US-2025316670-A1
Application number	US-202519241645-A
Country	US
Kind code	A1
Filing date	Jun 18, 2025
Priority date	Mar 23, 2018
Publication date	Oct 9, 2025
Grant date	—

Abstract

In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

First claim

What is claimed is:

1 . A package comprising:
a first package component comprising a first conductive feature and a second conductive feature; a second package component comprising a third conductive feature and a fourth conductive feature; a first conductive connector electrically coupling the third conductive feature to the first conductive feature, the first package component and the second package component being separated by a first distance adjacent the first conductive connector, the first conductive connector including a first conductive material, a first inter-metallic compound (IMC) between the first conductive material and the first conductive feature, and a second IMC between the first conductive material and the third conductive feature; and a second conductive connector electrically coupling the fourth conductive feature to the second conductive feature, the first package component and the second package component being separated by a second distance adjacent the second conductive connector, the second conductive connector including a second conductive material, a third IMC between the second conductive material and the second conductive feature, and a fourth IMC between the second conductive material and the fourth conductive feature, wherein a thickness of the first conductive material is less than a thickness of the second conductive material.

2 . The package of claim 1 , wherein the first distance and the second distance are equal.

3 . The package of claim 1 , wherein the first conductive connector is closer to an edge of the first package component than the second conductive connector.

4 . The package of claim 1 , wherein a first thickness of the first IMC is greater than a second thickness of the third IMC.

5 . The package of claim 4 , wherein a ratio of the first thickness to the second thickness is in a range of 1.2 to 2.0.

6 . The package of claim 4 , wherein the first thickness is in a range of 7.2 μm to 8 μm.

7 . The package of claim 4 , wherein the second thickness is in a range of 4 μm to 6 μm.

8 . A package structure comprising:
a first package comprising a first conductive feature and a second conductive feature; a second package comprising a third conductive feature and a fourth conductive feature; a first conductive element joining the first conductive feature to the third conductive feature; a first inter-metallic compound (IMC) formed between the first conductive element and the first conductive feature, the first IMC having a first thickness; a second conductive element joining the second conductive feature to the fourth conductive feature; and a second inter-metallic compound (IMC) formed between the second conductive element and the second conductive feature, the second IMC having a second thickness, the second thickness being greater than the first thickness.

9 . The package structure of claim 8 , wherein a thickness of the second conductive element is less than a thickness of the first conductive element.

10 . The package structure of claim 8 , wherein the first package comprises an integrated circuit die, an encapsulant along sidewalls of the integrated circuit die, a first through via in the encapsulant, and a second through via in the encapsulant, wherein the first conductive element is coupled to the first through via, wherein the second conductive element is coupled to the second through via.

11 . The package structure of claim 10 , wherein the first through via is closer to the integrated circuit die than the second through via.

12 . The package structure of claim 8 , wherein a ratio of the second thickness to the first thickness is in a range of 1.2 to 2.0.

13 . The package structure of claim 12 , wherein the second thickness is in a range of 7.2 μm to 8 μm.

14 . The package structure of claim 13 , wherein the first thickness is in a range of 4 μm to 6 μm.

15 . A package structure comprising:
a package substrate; a first package mounted on the package substrate, the first package including:
a first integrated circuit die;
a first encapsulant surrounding the first integrated circuit die; and
a first through via and a second through via extending through the first encapsulant;
a second package mounted on the first package; and a plurality of conductive connectors between the first package and the second package, the plurality of conductive connectors including a first conductive connector coupled to the first through via and a second conductive connector coupled to the second through via, the first conductive connector having first inter-metallic compound (IMC) region with a first thickness, the second conductive connector having a second IMC region with a second thickness, wherein the first thickness is greater than the second thickness.

16 . The package structure of claim 15 , wherein the first conductive connector and the second conductive connector have a same height.

17 . The package structure of claim 15 , wherein the second package comprises:
a redistribution structure; and a second integrated circuit die coupled to the redistribution structure, wherein the redistribution structure is between the second integrated circuit die and the first conductive connector.

18 . The package structure of claim 15 , wherein a width of the first package is equal to a width of the second package.

19 . The package structure of claim 15 , wherein the second conductive connector is closer to the first integrated circuit die than the first conductive connector.

20 . The package structure of claim 15 , wherein a ratio of the first thickness to the second thickness is in a range of 1.2 to 2.0.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pei Hao-Jan
• Lin Hsiu-Jen
• Chen Wei-Yu
• Chung Philip Yu-Shuan
• Cheng Chia-Shen
• Huang Kuei-Wei
• Hsieh Ching-Hua
• Liu Chung-Shi
• Yu Chen-Hua

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title