Semiconductor device, forming method and memory system

Patent metadata

Field	Value
Publication number	US-2025316593-A1
Application number	US-202418886982-A
Country	US
Kind code	A1
Filing date	Sep 16, 2024
Priority date	Apr 9, 2024
Publication date	Oct 9, 2025
Grant date	—

Abstract

Semiconductor devices, methods for forming such semiconductor devices, and systems including such semiconductor devices are provided. In one aspect, a semiconductor device includes a first semiconductor structure that includes a stack structure and a transistor. The stack structure includes first conductive layers and second conductive layers that are stacked alternately in a first direction. The transistor is disposed on one side of the stack structure and connected with one of the first conductive layers. The first semiconductor structure further includes a first connection structure extending through the stack structure in the first direction and connected to the second conductive layers.

First claim

What is claimed is:

1 . A semiconductor device, comprising a first semiconductor structure that comprises:
a stack structure and a transistor, wherein the stack structure comprises first conductive layers and second conductive layers stacked alternately in a first direction, and the transistor is on one side of the stack structure and connected with one of the first conductive layers; and a first connection structure extending through the stack structure in the first direction and connected to the second conductive layers.

2 . The semiconductor device of claim 1 , wherein the stack structure further comprises:
dielectric layers between the first conductive layers and the second conductive layers.

3 . The semiconductor device of claim 1 , wherein the first semiconductor structure further comprises:
a second connection structure extending through the stack structure in the first direction and respectively connected to the first conductive layers and the transistor.

4 . The semiconductor device of claim 3 , wherein the stack structure further comprises:
first isolation layers between the second connection structure and the second conductive layers.

5 . The semiconductor device of claim 3 , comprising a plurality of sets of second connection structures, each set of second connection structures being connected to a respective one of the first conductive layers.

6 . The semiconductor device of claim 1 , wherein the stack structure comprises at least two of the second conductive layers connected to the first connection structure.

7 . The semiconductor device of claim 6 , wherein the first connection structure is a slit structure extending in a second direction perpendicular to the first direction.

8 . The semiconductor device of claim 1 , comprising a plurality of sets of first connection structures, wherein the stack structure comprises a plurality of second conductive layers, each of the plurality of second conductive layers being connected to a respective set of first connection structures.

9 . The semiconductor device of claim 8 , wherein the first semiconductor structure further comprises:
an isolation structure extending through the stack structure in the first direction and extending in a second direction perpendicular to the first direction.

10 . The semiconductor device of claim 1 , wherein the transistor comprises a vertical transistor that comprises a semiconductor body extending in the first direction and a gate layer in contact with at least one side of the semiconductor body.

11 . The semiconductor device of claim 1 , further comprising:
a metal layer disposed on another side of the stack structure away from the transistor.

12 . The semiconductor device of claim 1 , further comprising:
a second semiconductor structure located on a side of the first semiconductor structure away from the transistor and integrated with the first semiconductor structure by hybrid bonding.

13 . A method of forming a semiconductor device, comprising:
forming a first semiconductor structure, comprising:
forming a semiconductor body of a transistor and a stack structure, wherein the stack structure comprises first sacrificial layers, first dielectric layers, second conductive layers, and second dielectric layers that are stacked alternately in a first direction;
forming a first electrode on the semiconductor body, the first electrode being one of a source and a drain of the transistor;
replacing the first sacrificial layers with first conductive layers, one of the first conductive layers being connected to the first electrode; and
forming a first connection structure connected to the second conductive layers and
extending through the stack structure.

14 . The method of claim 13 , wherein forming the first electrode on the semiconductor body comprises:
forming a connection hole extending through the stack structure to the semiconductor body in the first direction; forming first isolation layers and second isolation layers at an inner wall of the connection hole, wherein the first isolation layers isolate the second conductive layers, and the second isolation layers isolate the first sacrificial layers without connection relationship; and forming, in the connection hole, a second connection structure respectively connected to one of the first sacrificial layers and the first electrode.

15 . The method of claim 14 , wherein forming the connection hole extending through the stack structure to the semiconductor body in the first direction comprises:
forming an original slit extending through the stack structure in the first direction.

16 . The method of claim 15 , wherein, before forming, in the connection hole, the second connection structure connected to one of the first sacrificial layers and the first electrode respectively, the method further comprises:
depositing a second sacrificial layer in the connection hole and the original slit.

17 . The method of claim 16 , wherein forming, in the connection hole, the second connection structure connected to one of the first sacrificial layers and the first electrode respectively comprises:
removing the second sacrificial layer deposited in the connection hole and filling the connection hole to form the second connection structure.

18 . A memory system, comprising:
a semiconductor device; and a controller,
wherein the semiconductor device comprises a first semiconductor structure comprising a stack structure, a transistor and a first connection structure, wherein the stack structure comprises first conductive layers and second conductive layers stacked alternately along a first direction, the transistor is disposed on one side of the stack structure and connected with one of the first conductive layers, and the first connection structure extends through the stack structure in the first direction and is connected to the second conductive layers; and
a bit line and a word line connected to the transistor respectively,
wherein the controller is coupled to the semiconductor device and configured to control the semiconductor device.

19 . The memory system of claim 18 , wherein the stack structure further comprises:
dielectric layers between the first conductive layers and the second conductive layers.

20 . The memory system of claim 18 , wherein the first semiconductor structure further comprises:
a second connection structure extending through the stack structure in the first direction and connected to the first conductive layers and the transistor, respectively.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Jiajia
• Xu Zongke
• Yuan Bin
• Xu Wei
• Huo Zongliang
• Gong Fan
• Li Beibei
• Sun Chao

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/48

  Data lines or contacts therefor · CPC title

• H10B12/30 Primary

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title