Multi-Gate Transistor Channel Height Adjustment

Patent metadata

Field	Value
Publication number	US-2025311387-A1
Application number	US-202519236179-A
Country	US
Kind code	A1
Filing date	Jun 12, 2025
Priority date	Jul 9, 2021
Publication date	Oct 2, 2025
Grant date	—

Abstract

A semiconductor device includes a semiconductor substrate, first channel layers vertically stacked over a first fin-shaped base protruding from the semiconductor substrate, second channel layers vertically stacked over a second fin-shaped base protruding from the semiconductor substrate, an isolation feature extending from a sidewall of the first fin-shaped base to a sidewall of the second fin-shaped base, and a gate structure wrapping around each of the first and second channel layers. A top surface of the isolation feature intersects the sidewall of the first fin-shaped base at a first position and intersects the sidewall of the second fin-shaped base at a second position higher than the first position.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate; a plurality of first channel layers vertically stacked over a first fin-shaped base protruding from the semiconductor substrate; a plurality of second channel layers vertically stacked over a second fin-shaped base protruding from the semiconductor substrate; an isolation feature extending from a sidewall of the first fin-shaped base to a sidewall of the second fin-shaped base; and a gate structure wrapping around each of the first and second channel layers, wherein a top surface of the isolation feature intersects the sidewall of the first fin-shaped base at a first position and intersects the sidewall of the second fin-shaped base at a second position higher than the first position.

2 . The semiconductor device of claim 1 , wherein a bottom portion of the first fin-shaped base has a dopant concentration greater than that of a bottom portion of the second fin-shaped base.

3 . The semiconductor device of claim 2 , wherein the first channel layers are part of an n-type transistor and the second channel layers are part of a p-type transistor, and wherein the dopant concentration is of a p-type dopant.

4 . The semiconductor device of claim 1 , wherein the isolation feature includes a first portion proximal to the sidewall of the first fin-shaped base and a second portion proximal to the sidewall of the second fin-shaped base, and the first portion of the isolation feature includes a higher dopant concentration than the second portion of the isolation feature.

5 . The semiconductor device of claim 1 , wherein the second position is higher than the first position for about 5 nm to about 25 nm.

6 . The semiconductor device of claim 1 , wherein the top surface of the isolation feature forms a first sidewall angle with respect to the sidewall of the first fin-shaped base and a second sidewall angle with respect to the sidewall of the second fin-shaped base, wherein the first sidewall angle is larger than the second sidewall angle.

7 . The semiconductor device of claim 6 , wherein the first sidewall angle is larger than about 55 degrees, and the second sidewall angle is less than about 45 degrees.

8 . The semiconductor device of claim 1 , wherein the top surface of the isolation feature has a first concave profile proximal to the first fin-shaped base and a second concave profile proximal to the second fin-shaped base, the first and second concave profiles have different concave depths.

9 . The semiconductor device of claim 1 , further comprising:
a first liner interposing the isolation feature and the sidewall of the first fin-shaped base; and a second liner interposing the isolation feature and the sidewall of the second fin-shaped base, wherein the first liner and the second liner include different material compositions.

10 . A semiconductor device, comprising:
a substrate; an isolation feature over the substrate; a first fin-shaped structure protruding from the substrate and through the isolation feature; a second fin-shaped structure protruding from the substrate and through the isolation feature; and a gate structure covering a top surface of the first fin-shaped structure and a top surface of the second fin-shaped structure, wherein a portion of the isolation feature disposed between the first and second fin-shaped structures has a first top surface proximal to the first fin-shaped structure and a second top surface proximal to the second fin-shaped structure, and the first top surface is lower than the second top surface.

11 . The semiconductor device of claim 10 , wherein the first top surface of the isolation feature forms a first sidewall angle with respect to a sidewall of the first fin-shaped structure, the second top surface of the isolation feature forms a second sidewall angle with respect to a sidewall of the second fin-shaped structure, wherein the first sidewall angle different from the second sidewall angle.

12 . The semiconductor device of claim 10 , further comprising:
a doped region in the substrate and under the first fin-shaped structure, wherein the second fin-shaped structure is laterally spaced away from the doped region.

13 . The semiconductor device of claim 12 , wherein a top surface of the doped region is above a bottom surface of the isolation feature.

14 . The semiconductor device of claim 12 , further comprising:
an anti-punch-through region under the doped region.

15 . The semiconductor device of claim 14 , wherein the doped region has a bottom portion overlapped with a top portion of the anti-punch-through region.

16 . The semiconductor device of claim 10 , wherein a first vertical distance between a top surface of the first fin-shaped structure and a lowest point of the first top surface of the isolation feature is greater than a second vertical distance between a top surface of the second fin-shaped structure and a lowest point of the second top surface of the isolation feature.

17 . A semiconductor device, comprising:
a substrate; a first fin-shaped structure protruding from the substrate; a second fin-shaped structure protruding from the substrate; and an isolation feature extending from a sidewall of the first fin-shaped structure to a sidewall of the second fin-shaped structure, wherein a top surface of the isolation feature intersects the sidewall of the first fin-shaped structure at a first position and intersects the sidewall of the second fin-shaped structure at a second position, wherein a first vertical distance between a top surface of the first fin-shaped structure and the first position is greater than a second vertical distance between a top surface of the second fin-shaped structure and the second position.

18 . The semiconductor device of claim 17 , wherein the first vertical distance is greater than the second vertical distance for about 5 nm to about 25 nm.

19 . The semiconductor device of claim 17 , wherein the isolation feature includes a first region proximal to the sidewall of the first fin-shaped structure and a second region proximal to the sidewall of the second fin-shaped structure, and the first region of the isolation feature includes a dopant concentration greater than that of the second region of the isolation feature.

20 . The semiconductor device of claim 19 , wherein the first fin-shaped structure is part of a first transistor of a first conductivity type, the second fin-shaped structure is part of a second transistor of a second conductivity type opposing the first conductivity type, and the dopant concentration is of a dopant of the second conductivity type.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kao Pei-Ling
• Lin You-Ting
• Chang Chih-Chung
• Kuo Jiun-Ming
• Peng Yuan-Ching

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10P14/61

  using masks · CPC title