Fin field-effect transistor device and method

Patent metadata

Field	Value
Publication number	US-2025311350-A1
Application number	US-202519232448-A
Country	US
Kind code	A1
Filing date	Jun 9, 2025
Priority date	Jul 9, 2021
Publication date	Oct 2, 2025
Grant date	—

Abstract

A method includes depositing an interlayer dielectric (ILD) over a source/drain region, implanting impurities into a portion of the ILD, recessing the portion of the ILD to form a trench, forming spacers on sidewalls of the trench, the spacers including a spacer material, forming a source/drain contact in the trench and removing the spacers and the portion of the ILD with an etching process to form an air-gap, the air-gap disposed under and along sidewalls of the source/drain contact, where the etching process selectively etches the spacer material and the impurity.

First claim

What is claimed is:

1 . A device comprising:
a first fin protruding from a semiconductor substrate; a first source/drain region in the first fin; a second fin protruding from the semiconductor substrate; a second source/drain region in the second fin; a source/drain contact overlapping the first source/drain region and the second source/drain region, the source/drain contact connected to the first source/drain region; and an air-gap having a first portion extending along sidewalls of the source/drain contact and having a second portion under the source/drain contact, wherein the air-gap separates the source/drain contact from the second source/drain region.

2 . The device of claim 1 , further comprising a conductive line electrically connected to the first source/drain region through the source/drain contact, wherein the conductive line overlaps and has a same orientation as the second fin.

3 . The device of claim 1 , further comprising a dielectric layer over the air-gap and the source/drain contact, the dielectric layer sealing the air-gap.

4 . The device of claim 3 , further comprising:
a gate structure over the first fin and the second fin; and a gate mask disposed between the gate structure and the dielectric layer, wherein a top surface of the gate mask, a top surface of the source/drain contact, and a topmost point of the air-gap are at the same level.

5 . The device of claim 4 , wherein the gate structure comprises curved top surfaces.

6 . The device of claim 1 , further comprising a dielectric spacer disposed between the sidewalls of the source/drain contact and the first portion of the air-gap.

7 . The device of claim 6 , wherein the dielectric spacer comprises silicon nitride.

8 . A device comprising:
a source/drain contact overlapping a first source/drain region in a first fin and a second source/drain region in a second fin, wherein the source/drain contact is electrically connected to the first source/drain region; and an air-gap having a first portion disposed under the source/drain contact, wherein the first portion of the air-gap isolates the source/drain contact from the second source/drain region.

9 . The device of claim 8 , wherein the air-gap further comprises a second portion extending along sidewalls of the source/drain contact.

10 . The device of claim 9 , further comprising a dielectric spacer disposed between the sidewalls of the source/drain contact and the second portion of the air-gap.

11 . The device of claim 9 , further comprising a gate structure over the first fin and the second fin, wherein the gate structure comprises curved top surfaces.

12 . The device of claim 9 , further comprising a gate structure over the first fin and the second fin, wherein the gate structure comprises concave top surfaces.

13 . The device of claim 12 , further comprising:
a dielectric layer over the gate structure and the air-gap; and a gate mask disposed between the gate structure and the dielectric layer, wherein a material of the gate mask is different from a material of the dielectric layer.

14 . The device of claim 13 , wherein the material of the gate mask comprises silicon nitride.

15 . A device comprising:
a first source/drain region in a first fin; a source/drain contact overlapping the first source/drain region; an air-gap having a first portion extending along sidewalls of the source/drain contact and having a second portion under the source/drain contact, wherein the air-gap isolates the source/drain contact from the first source/drain region; and a gate structure over the first fin, wherein the gate structure comprises curved top surfaces.

16 . The device of claim 15 , further comprising a dielectric layer over the air-gap, the gate structure, and the source/drain contact, the dielectric layer sealing the air-gap.

17 . The device of claim 16 , further comprising a gate mask disposed between the gate structure and the dielectric layer, wherein a material of the gate mask is different from a material of the dielectric layer.

18 . The device of claim 15 , further comprising a second source/drain region in a second fin, wherein the source/drain contact overlaps and is electrically connected to the second source/drain region.

19 . The device of claim 15 , further comprising a dielectric spacer disposed between the sidewalls of the source/drain contact and the first portion of the air-gap.

20 . The device of claim 19 , wherein the dielectric spacer comprises silicon nitride.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeong Sai-Hooi
• LEE Kai-Hsuan
• Chui Chi On

Classifications

• H10P50/283 Primary

  by chemical means · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title