Discontinuous high dielectric constant (hk) layer
US-2026096147-A1 · Apr 2, 2026 · US
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Sarkar Debarghya patents
Sarkar Debarghya is listed as an inventor on 28 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Sarkar Debarghya |
| Total patents | 28 |
| First publication | May 22, 2025 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Stacked fet with flexible inter-epi dielectric thickness
US-2026096199-A1 · Apr 2, 2026 · US
Stacked transistors with work function material
US-2026068307-A1 · Mar 5, 2026 · US
Fork sheet field effect transistor with increased electrostatic control
US-2026059830-A1 · Feb 26, 2026 · US
Damascene interconnects with bilayer liner
US-2026047411-A1 · Feb 12, 2026 · US
Stacked fet with metallic source/drain contact
US-2026047133-A1 · Feb 12, 2026 · US
Stacked semiconductor structure with opposite polarity transistors
US-2025386592-A1 · Dec 18, 2025 · US
Sidewall pinch-off of work function metal
US-2025380501-A1 · Dec 11, 2025 · US
Stacked field-effect transistors with asymmetric source/drain regions
US-2025380455-A1 · Dec 11, 2025 · US
Dog bone channel fet with no inner spacer
US-2025380463-A1 · Dec 11, 2025 · US
Recent patents
Latest publications not already listed above.
Stacked transistors with vertically staggered contact vias
US-2025359320-A1 · Nov 20, 2025 · US
Backside dielectric plug
US-2025344444-A1 · Nov 6, 2025 · US
Stacked transistors with discontinuous high-k on vertical gate spacers
US-2025338615-A1 · Oct 30, 2025 · US
Scaled stacked fet using combined structures in adjacent cells
US-2025324692-A1 · Oct 16, 2025 · US
3-transistor footprint stacked sram
US-2025318100-A1 · Oct 9, 2025 · US
Stacked field effect transistors
US-2025311319-A1 · Oct 2, 2025 · US
Directional conductor interconnect with embedded via
US-2025309099-A1 · Oct 2, 2025 · US
Epi region with trench extension and wraparound contact
US-2025311320-A1 · Oct 2, 2025 · US
Stacked gate-all-around transistor and forksheet transistor
US-2025311417-A1 · Oct 2, 2025 · US
Backside gate tie-down in backside power distribution network (bspdn) architecture
US-2025309116-A1 · Oct 2, 2025 · US
Semiconductor device with dielectric thermal conductor
US-2025301791-A1 · Sep 25, 2025 · US
Scaled Two-Transistor-One-Capacitor Semiconductor Device
US-2025301659-A1 · Sep 25, 2025 · US
Self-aligned isolation layer for stacked field-effect transistors
US-2025294887-A1 · Sep 18, 2025 · US
Stacked field effect transistor with epitaxy cut for source/drain contact
US-2025239521-A1 · Jul 24, 2025 · US
Backside dielectric cap
US-2025192048-A1 · Jun 12, 2025 · US
Offset staggered stacked field effect transistor (sfet) devices
US-2025185345-A1 · Jun 5, 2025 · US
Stacked nanosheet devices with interfacial layers
US-2025185355-A1 · Jun 5, 2025 · US
Stacked field-effect transistor device with backside cut for top source/drain access
US-2025167118-A1 · May 22, 2025 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 28 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D62/121 | 19 |
| H10D30/6735 | 18 |
| H10D30/6757 | 18 |
| H10D30/43 | 18 |
| H10D84/038 | 17 |