Structures including metal-insulator-metal (mim) capacitors with voids

Patent metadata

Field	Value
Publication number	US-2025311253-A1
Application number	US-202418624085-A
Country	US
Kind code	A1
Filing date	Apr 1, 2024
Priority date	Apr 1, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

The embodiments herein relate to structures of MIM capacitors including a sealed void and methods of forming the same. According to an aspect of the present disclosure, a structure is provided. The structure includes a MIM capacitor having a first electrode and a second electrode over the first electrode. A conductive via is laterally adjacent to the second electrode and electrically connected to the first electrode. A void extends around an outer perimeter of the second electrode.

First claim

What is claimed is:

1 . A structure, comprising:
a metal-insulator-metal (MIM) capacitor including a first electrode and a second electrode over the first electrode; a conductive via laterally adjacent to the second electrode and electrically connected to the first electrode; and a void extends around an outer perimeter of the second electrode.

2 . The structure of claim 1 , wherein the first electrode comprises an outer perimeter, and the outer perimeter of the second electrode is within the outer perimeter of the first electrode.

3 . The structure of claim 2 , wherein the void is laterally between the conductive via and the second electrode.

4 . The structure of claim 3 , wherein the void is within the outer perimeter of the first electrode.

5 . The structure of claim 1 , wherein the MIM capacitor further comprises a capacitor insulator between the first electrode and the second electrode, further comprising a dielectric layer on the second electrode, wherein the void is surrounded by the dielectric layer from above and the capacitor insulator from below.

6 . The structure of claim 5 , further comprising a first spacer component, and the first spacer component is laterally between the conductive via and the void.

7 . The structure of claim 6 , further comprising a second spacer component laterally surrounding the first spacer component and the first electrode.

8 . The structure of claim 7 , wherein the second spacer component includes an outer side surface coplanar with a side surface of the first electrode.

9 . The structure of claim 8 , wherein the first spacer component has an upper surface, the second spacer component has an upper surface, and the dielectric layer has an upper surface, wherein the upper surfaces of the first spacer component and the second spacer component are coplanar with the upper surface of the dielectric layer.

10 . The structure of claim 8 , wherein the conductive via includes a first protrusion, and the first protrusion extends towards the second electrode.

11 . The structure of claim 10 , wherein the first protrusion laterally contacts the first spacer component.

12 . The structure of claim 11 , wherein the conductive via further comprises a second protrusion at an opposite side of the first protrusion, and the second protrusion laterally contacts the second spacer component.

13 . A method, comprising:
forming a metal-insulator-metal (MIM) capacitor including a first electrode and a second electrode over the first electrode; forming a conductive via laterally adjacent to the first electrode and electrically connected to the first electrode; and forming a void extending around an outer perimeter of the second electrode.

14 . The method of claim 13 , wherein the first electrode comprises an upper surface area and the second electrode comprises a bottom surface area that is smaller than the upper surface area of the first electrode.

15 . The method of claim 13 , wherein forming the MIM capacitor comprises using a single mask.

16 . The method of claim 15 , further comprising:
depositing a first conductor layer; depositing a second conductor layer over the first conductor layer, depositing a dielectric layer on the second conductor layer; using the mask to form an opening at least through the dielectric layer and the second conductor layer; and recessing the second conductor layer relative to the first conductor layer to define a void that is offset laterally from the opening to form the second electrode.

17 . The method of claim 16 , further comprising depositing a spacer material over the first conductor layer and filling the opening to seal the void laterally between the spacer material and the second electrode.

18 . The method of claim 17 , further comprising forming a spacer from the spacer material having an upper surface coplanar with an upper surface of the dielectric layer.

19 . The method of claim 18 , wherein the forming of coplanar upper surfaces of the spacer and the dielectric layer also forms the first electrode of the MIM capacitor.

20 . The method of claim 19 , wherein the forming of the first electrode of the MIM capacitor uses a blanket etching process.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• KHOR Ee Jan
• Yi Wanbing

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71 Primary

  using masks for conductive or resistive materials · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L21/31144

  Electricity · mapped topic