Memory device including a core-side charge trapping material layer and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2025301654-A1
Application number	US-202418989549-A
Country	US
Kind code	A1
Filing date	Dec 20, 2024
Priority date	Mar 25, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and including, from outside to inside, a memory film including a vertical stack of charge storage elements located at levels of the electrically conductive layers, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.

First claim

What is claimed is:

1 . A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a memory film comprising a vertical stack of charge storage elements located at levels of the electrically conductive layers, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.

2 . The memory device of claim 1 , wherein:
a first subset of the electrically conductive layers are laterally offset from the core-side charge trapping material layer by a first lateral offset distance; and a second subset of the electrically conductive layers are laterally offset from the core-side charge trapping material layer by a second lateral offset distance that is greater than the first lateral offset distance.

3 . The memory device of claim 2 , wherein:
the first subset of the electrically conductive layers comprises word lines; and the second subset of the electrically conductive layers comprises at least one select gate electrode.

4 . The memory device of claim 3 , wherein the second subset of the electrically conductive layers comprises at least one drain-side select gate electrode overlying the word lines.

5 . The memory device of claim 3 , wherein the second subset of the electrically conductive layers comprises at least one source-side select gate electrode underlying the word lines

6 . The memory device of claim 2 , wherein:
the first subset of the electrically conductive layers comprises a respective first cylindrical sidewall that is laterally offset from a vertical axis passing through a geometrical center by the first lateral offset distance; and the second subset of the electrically conductive layers comprises a respective second cylindrical sidewall that is laterally offset from the vertical axis by the second lateral offset distance.

7 . The memory device of claim 2 , wherein the vertical semiconductor channel comprises an outer semiconductor sidewall having a first laterally undulating vertical cross-sectional profile at each level of the second subset of the electrically conductive layers.

8 . The memory device of claim 7 , wherein the vertical semiconductor channel further comprises an inner semiconductor sidewall having a second laterally undulating vertical cross-sectional profile at each level of the second subset of the electrically conductive layers.

9 . The memory device of claim 7 , wherein the vertical semiconductor channel further comprises an inner semiconductor sidewall that vertically extends straight through each of the electrically conductive layers.

10 . The memory device of claim 7 , wherein the memory opening fill structure further comprises a dielectric liner located between the vertical semiconductor channel and the core-side charge trapping material layer.

11 . The memory device of claim 10 , wherein the dielectric liner comprises:
an outer dielectric sidewall having a third laterally undulating vertical cross-sectional profile at each level of the second subset of the electrically conductive layers; and an inner dielectric sidewall that vertically extends straight through each of the electrically conductive layers.

12 . The memory device of claim 7 , wherein a lateral distance between the outer semiconductor sidewall and an inner semiconductor sidewall of the vertical semiconductor channel is greater at each level of the second subset of the electrically conductive layers than at each level of the first subset of the electrically conductive layers.

13 . The memory device of claim 2 , wherein the memory film comprises:
a blocking dielectric layer; a charge storage layer located inside the blocking dielectric layer, wherein the vertical stack of charge storage elements comprises portions of the charge storage layer located at the levels of the electrically conductive layers; and a tunneling dielectric layer located between the charge storage layer and the vertical semiconductor channel, wherein each of the blocking dielectric layer, the charge storage layer, and the tunneling dielectric layer has a respective vertical cross-sectional profile including a respective lateral undulation at levels of the second subset of the electrically conductive layers.

14 . The memory device of claim 2 , wherein:
the memory opening fill structure further comprises a tubular spacer interposed between the vertical semiconductor channel and an upper portion of the core-side charge trapping material layer; and the core-side charge trapping material layer comprises:
a lower cylindrical portion that underlies an annular bottom surface of the tubular spacer and is offset from the first subset of the electrically conductive layers by the first lateral offset distance; and
an upper cylindrical portion that is laterally surrounded by the tubular spacer and is offset from the second subset of the electrically conductive layers by the second lateral offset distance.

15 . The memory device of claim 14 , wherein the dielectric core comprises:
a lower dielectric core portion having a first lateral extent; and an upper dielectric core portion having a second lateral extent that is less than the first lateral extent, wherein an annular top surface of the lower dielectric core portion comprises an inner periphery that is adjoined to a bottom periphery of the upper dielectric core portion and an outer periphery that is adjoined to a top periphery of the lower dielectric core portion.

16 . A method of forming a device structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate, wherein the sacrificial material layers comprise lower-etch-rate first silicon nitride material layers and at least one higher-etch-rate second silicon nitride material layer; forming a memory opening through the alternating stack; laterally recessing the at least one higher-etch-rate second silicon nitride material layer at a higher etch rate than the lower-etch-rate first silicon nitride material layers; forming a memory film, a vertical semiconductor channel, a core-side charge trapping material layer, and a dielectric core in the memory opening; and replacing the sacrificial material layers at least with electrically conductive layers.

17 . The method of claim 16 , wherein:
the lower-etch-rate first silicon nitride material layers comprise silicon nitride layers that are not doped with oxygen; the higher-etch-rate second silicon nitride material layers comprise silicon nitride layers that are doped with oxygen.

18 . The method of claim 16 , wherein the memory film has a greater lateral extent at each level of the at least one higher-etch-rate second silicon nitride material layer than at levels of the lower-etch-rate first silicon nitride material layers.

19 . The method of claim 16 , further comprising forming a tubular spacer in an upper portion of the memory opening after formation of the memory film.

20 . The method of claim 16 , wherein:
the tubular spacer comprises a semiconductor material that is formed directly on an upper portion of an inner sidewall of the vertical semiconductor channel, and the method further comprises forming a dielectric liner on an inner sidewall

Assignees

• Sandisk Technologies Llc

Inventors

• Gyakushi Takayuki
• Sakotsubo Yukihiro
• Kudo Takashi
• ZOU Liumin
• Osawa Kohei
• Mizutani Motoki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title