Memory device including a core-side charge trapping material layer and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2025301643-A1
Application number	US-202418787367-A
Country	US
Kind code	A1
Filing date	Jul 29, 2024
Priority date	Mar 25, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes, from outside to inside, a memory film, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.

First claim

What is claimed is:

1 . A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a memory film, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.

2 . The memory device of claim 1 , wherein the core-side charge trapping material layer does not vertically extend through a second subset of the electrically conductive layers.

3 . The memory device of claim 2 , wherein the second subset of the electrically conductive layers comprises a topmost electrically conductive layer of the electrically conductive layers.

4 . The memory device of claim 3 , wherein the second subset of the electrically conductive layers comprises at least two drain side select gate electrodes.

5 . The memory device of claim 4 , wherein the second subset of the electrically conductive layers further comprises at least one dummy word line, and the first subset of the electrically conductive layers comprises word lines.

6 . The memory device of claim 2 , wherein the second subset of the electrically conductive layers comprises a bottommost electrically conductive layer of the electrically conductive layers.

7 . The memory device of claim 2 , wherein the second subset of the electrically conductive layers comprises at least two source side select gate electrodes.

8 . The memory device of claim 2 , wherein the second subset of the electrically conductive layers comprises all source side select gate electrodes and all drain side select gate electrodes, and the first subset of the electrically conductive layers comprises active word lines.

9 . The memory device of claim 1 , wherein the dielectric core comprises:
a primary dielectric core portion that is laterally surrounded by the core-side charge trapping material layer; and a complementary dielectric core portion that overlies or underlies the primary dielectric core portion.

10 . The memory device of claim 9 , wherein:
the memory opening fill structure comprises a drain region contacting a first end portion of the vertical semiconductor channel; and the complementary dielectric core portion contacts the drain region.

11 . The memory device of claim 10 , further comprising:
additional memory openings vertically extending through the alternating stack; additional memory opening fill structures located in the additional memory openings and comprising a respective additional memory film and a respective additional vertical semiconductor channel; and a source layer contacting second end portions of the vertical semiconductor channel and the additional vertical semiconductor channels.

12 . The memory device of claim 11 , wherein the complementary dielectric core portion contacts the source layer.

13 . The memory device of claim 1 , wherein:
the dielectric core comprises silicon oxide; and the core-side charge trapping material layer comprises silicon nitride, aluminum oxide, or silicon oxynitride.

14 . The memory device of claim 1 , wherein:
the dielectric core comprises silicon oxide; and the core-side charge trapping material layer comprises a layer stack including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer located between the first and the second silicon nitride layers.

15 . The memory device of claim 1 , further comprising a dielectric liner located between the core-side charge trapping material layer and the vertical semiconductor channel, wherein:
the memory film comprises a layer stack that comprises a tunneling dielectric layer in contact with an outer sidewall of the vertical semiconductor channel, a charge storage layer in contact with an outer sidewall of the tunneling dielectric layer, and a blocking dielectric layer in contact with an outer sidewall of the charge storage layer.

16 . A method of operating the memory device of claim 1 , comprising erasing the memory device by applying an erase voltage to the memory device to move electrons from the memory film through the vertical semiconductor channel into the core-side charge trapping material layer.

17 . A method of forming a memory device, comprising:
forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers; forming a memory opening through the alternating stack; forming a memory film, a vertical semiconductor channel, a core-side charge trapping material layer, and a primary dielectric core portion; reducing vertical extents of the core-side charge trapping material layer and the primary dielectric core portion at least by a sum of a thickness of one of the insulating layers and a thickness of one of the spacer material layers; and forming a complementary dielectric core portion on the primary dielectric core portion within a volume that is laterally surrounded by a cylindrical segment of an inner sidewall of the vertical semiconductor channel in the memory opening.

18 . The method of claim 17 , further comprising forming a drain region on the complementary dielectric core portion and on a first end portion of the vertical semiconductor channel.

19 . The method of claim 17 , further comprising forming a source layer on the complementary dielectric core portion and on a second end portion of the vertical semiconductor channel.

20 . The method of claim 17 , wherein:
the primary dielectric core comprises silicon oxide; the complementary dielectric core comprises silicon oxide; the core-side charge trapping material layer comprises silicon nitride, aluminum oxide, or silicon oxynitride; and the vertical extent of the core-side charge trapping material layer is reduced such that the core-side charge trapping material layer vertically extends through a first subset of the electrically conductive layers and does not vertically extend through a second subset of the electrically conductive layers.

Assignees

• Sandisk Technologies Llc

Inventors

• Gyakushi Takayuki
• Sakotsubo Yukihiro
• Kudo Takashi
• ZOU Liumin
• Osawa Kohei
• Mizutani Motoki

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title