Power chip package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025293201-A1
Application number	US-202418666844-A
Country	US
Kind code	A1
Filing date	May 17, 2024
Priority date	Mar 14, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

A power chip package structure and a manufacturing method thereof are disclosed. The power chip package structure includes a carrier, a self-correction layer, a conductive paste, and a power chip. The carrier includes a ceramic board and an inner metal layer that is formed on the ceramic board and that has a connection pad. The self-correction layer is formed on the inner metal layer, and the self-correction layer and the connection pad jointly define a slot. The self-correction layer includes a glue body and a plurality of elastic spacers covered by the glue body. The conductive paste is filled into the slot. The power chip includes a chip body disposed on the self-correction layer and a bonding pad that is formed on the chip body. The bonding pad is connected to the conductive paste, such that the power chip is electrically coupled to the carrier.

First claim

What is claimed is:

1 . A method for manufacturing a power chip package structure, comprising:
a pre-step: providing a first carrier, including a first ceramic board and a first inner metal layer formed on an inner plate surface of the first ceramic board, wherein the first inner metal layer comprises at least one first connection pad; a forming step: forming a first self-correction layer on the first inner metal layer, which comprises at least one first slot exposing the at least one first connection pad, wherein the first self-correction layer comprises a first glue body in a partially-cured state and a plurality of first elastic spacers disposed in the first glue body; a filling step: filling at least one first conductive paste into the at least one first slot; a chip placement step: using a jig to place a power chip on the first self-correction layer and the at least one first conductive paste, so that the at least one first bonding pad of the power chip is connected to the at least one first conductive paste, and at least one of the plurality of first elastic spacers is compressed and deformed by the power chip; a self-correction step: removing the jig to restore the compressed and deformed at least one of the plurality of first elastic spacers to its original shape, thereby pushing and moving the power chip to a preset position; and a curing step: sintering the first conductive paste and curing the first glue body to fix the power chip to the at least one first conductive paste and the first self-correction layer.

2 . The method according to claim 1 , wherein number of the at least one first connection pad, number of the at least one first slot, number of the at least one first bonding pad, and number of the at least one first conductive paste are two for each.

3 . The method according to claim 1 , wherein in the pre-step, the first inner metal layer is formed with at least one gap surrounding the at least one first connection pad, and in the forming step, the first glue body fills the at least one gap.

4 . The method according to claim 1 , wherein the first glue body is heated during the chip placement step so that fluidity of the first glue body in the self-correction step is higher than fluidity of the first glue body in the forming step.

5 . The method according to claim 1 , wherein each of the plurality of first elastic spacers is an elastic ball made of polymer material, and the at least one first conductive paste is a sintering silver paste.

6 . The method according to claim 5 , wherein top edges of the plurality of elastic balls are substantially aligned with a top surface of the first glue body and are in contact with the power chip.

7 . The method according to claim 1 , wherein the first carrier is a direct bonded copper (DBC), a direct plated copper (DPC), or an active metal brazing (AMB) ceramic substrate and includes a first outer metal layer, and the first inner metal layer and the first outer metal layer are respectively sintered and fixed to the inner plate surface and an outer plate surface of the first ceramic board.

8 . A power chip package structure, comprising:
a first carrier comprising a first ceramic board and a first inner metal layer formed on an inner plate surface of the first ceramic board, wherein the first inner metal layer comprises at least one first connection pad; a first self-correction layer formed on the first inner metal layer, wherein the first self-correction layer and at least one of the first connection pads jointly form at least one first slot, wherein the first self-correction layer comprises a first glue body and a plurality of first elastic spacers disposed in the first glue body; at least one first conductive paste filled into the at least one first slot; and a power chip, comprising: a chip body disposed on the first self-correction layer; and at least one first bonding pad formed on a first surface of the chip body, wherein the at least one first bonding pad is connected to the at least one first conductive paste, so that the power chip is electrically coupled to the first carrier.

9 . The power chip package structure according to claim 8 , wherein each of the first elastic spacers is an elastic ball made of polymer material, and the at least one first conductive paste is a sintering silver paste.

10 . The power chip package structure according to claim 9 , wherein top edges of the plurality of elastic spacers are substantially aligned with a top surface of the first glue body and are in contact with the first surface of the power chip.

11 . The power chip package structure according to claim 8 , wherein number of the at least one first connection pad, number of the at least one first slot, number of the at least one first bonding pad, and number of the at least one first conductive paste are two for each, wherein the first inner metal layer comprises a thermal pad located between two said at least one first connection pads, and the first self-correction layer and the thermal pad jointly form a receiving slot; the power chip package structure comprises a thermal conductive paste filled into the receiving slot, and the power chip has a heat dissipation pad located between the two said at least one first bonding pads, and the heat dissipation pad is connected to the thermal conductive paste.

12 . The power chip package structure according to claim 8 further comprising:
a second carrier comprising a second ceramic board and a second inner metal layer formed on the inner plate surface of the second ceramic board, wherein the second inner metal layer comprises at least one second connection pad;
a second self-correction layer formed on the second inner metal layer, wherein the second self-correction layer and the at least one second connection pad jointly form at least one second slot, wherein the second self-correction layer comprises a second glue body and a plurality of second elastic spacers disposed in the second glue body; and
at least one second conductive paste filled into the at least one second slot;
wherein the power chip comprises at least one second bonding pad formed on a second surface of the chip body, and the second self-correction layer is disposed on the second surface of the chip body, wherein the at least one second bonding pad is connected to the at least one second conductive paste, so that the power chip is electrically coupled to the second carrier.

13 . The power chip package structure according to claim 12 , wherein the power chip package structure further comprises a plurality of pins that are spaced apart from each other around the power chip and clamped and fixed between the first carrier and the second carrier, wherein each of the plurality of pins is electrically coupled to the first carrier and the second carrier.

14 . The power chip package structure according to claim 12 , wherein the first surface of the power chip is completely covered by the first self-correction layer and the at least one first conductive paste, and the second surface of the power chip is completely covered by the second self-correction layer and the at least one second conductive paste.

15 . The power chip package structure according to claim 12 , wherein the first carrier and the second carrier are each a direct bonded copper (DBC), a direct plated copper (DPC), or an active metal brazing (AMB) ceramic substrate, wherein the first carrier comprises a first outer metal layer, and the second carrier comprises a second outer metal layer, wherein the first inner metal layer and the first outer metal layer are respectively sintere

Assignees

• Tong Hsing Electronic Industries Ltd

Inventors

• Hsieh Yu-Te
• Chao Wei-Chung
• Chen Yan-Wei
• Chiu Zzu-Chi

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/01308

  using permanent auxiliary members, e.g. using alignment marks · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/931

  Shapes of bond pads · CPC title