Cavity package

Patent metadata

Field	Value
Publication number	US-2025287720-A1
Application number	US-202519218121-A
Country	US
Kind code	A1
Filing date	May 23, 2025
Priority date	Apr 20, 2022
Publication date	Sep 11, 2025
Grant date	—

Abstract

A device may include a substrate including a first material stack and a second material stack disposed on the first material stack, the second material stack defining a cavity, the first material stack and the second material stack respectively including: at least one insulating material layer; and at least one conductive layer. A device may include a semiconductor die disposed in the cavity. A device may include a material enclosing the semiconductor die in the cavity.

First claim

What is claimed is:

1 . A package comprising:
a substrate including a first material stack and a second material stack disposed on the first material stack, the second material stack defining a cavity, the first material stack and the second material stack respectively including:
at least one insulating material layer; and
at least one conductive layer;
a semiconductor die disposed in the cavity; and a material enclosing the semiconductor die in the cavity.

2 . The package of claim 1 , wherein the material enclosing the semiconductor die in the cavity is an encapsulant material.

3 . The package of claim 2 , wherein the encapsulant material is an epoxy material.

4 . The package of claim 1 , wherein:
sidewalls of the cavity are defined by the second material stack; and a bottom surface of the cavity is defined by the first material stack.

5 . The package of claim 4 , wherein the semiconductor die is flip-chip bonded with solder bumps on the bottom surface of the cavity.

6 . The package of claim 4 , wherein the semiconductor die is surface mounted on the bottom surface of the cavity.

7 . A package comprising:
a substrate including a first material stack and a second material stack disposed on the first material stack, the second material stack defining a first cavity, the first material stack and the second material stack respectively including:
at least one insulating material layer; and
at least one conductive layer;
a dam material having vertical walls proximate a perimeter of the first cavity, the dam material defining a second cavity; a first semiconductor die disposed in the first cavity; a first material enclosing the first semiconductor die in the first cavity; a second semiconductor die disposed in the second cavity, the second semiconductor die being disposed on the first material enclosing the first cavity and an upper surface of the second material stack of the substrate; and a second material enclosing the second semiconductor die in the second cavity.

8 . The package of claim 7 , wherein:
the first material enclosing the first semiconductor die in the first cavity is an epoxy material filling the first cavity; and the second material enclosing the second semiconductor die in the second cavity is a transparent cover disposed on the dam material, the transparent cover having an anti-reflective coating.

9 . The package of claim 8 , wherein:
the first semiconductor die includes an application-specific integrated circuit (ASIC); and the second semiconductor die includes an image sensor.

10 . The package of claim 9 , wherein the image sensor includes at least one of a micro lens or filter assembly, the second semiconductor die is surface mounted in the second cavity with at the least one of the micro lens or filter assembly facing toward the transparent cover.

11 . The package of claim 8 , wherein the transparent cover and seals the second semiconductor die in a gaseous atmosphere.

12 . The package of claim 7 , wherein the second semiconductor die is surface mounted to a di-receiving surface in the second cavity.

13 . The package of claim 7 , wherein the second semiconductor die is wire bonded to at least one conductive trace or at least one conductive pad included in the substrate.

14 . The package of claim 7 , wherein the first semiconductor die is wire bonded to at least one conductive trace or at least one conductive pad included in the substrate.

15 . The package of claim 7 , wherein the first semiconductor die is flip-chip bonded with solder bumps on a bottom surface of the first cavity.

16 . A package comprising:
a substrate having a first cavity disposed below a second cavity, the second cavity having an open top, the substrate including:
a first material stack;
a second material stack disposed on the first material stack, the second material stack defining the first cavity, the first material stack and the second material stack respectively including:
at least one insulating material layer; and
at least one conductive layer; and

a dam material having vertical walls proximate a perimeter of the first cavity, the dam material defining the second cavity;
a first semiconductor die disposed in the first cavity; a first material enclosing the first semiconductor die in the first cavity; a second semiconductor die disposed in the second cavity, the second semiconductor die being disposed on the first material enclosing the first cavity and an upper surface of the second material stack of the substrate; and a second material enclosing the second semiconductor die in the second cavity.

17 . The package of claim 16 , wherein the first material enclosing the first semiconductor die in the first cavity is an epoxy material filling the first cavity.

18 . The package of claim 16 , wherein:
the second semiconductor die includes a complementary metal-oxide-semiconductor image sensor; and the second material enclosing the second semiconductor die in the second cavity includes a transparent cover disposed on the dam material and covering the open top of the second cavity.

19 . The package of claim 18 , wherein the complementary metal-oxide-semiconductor image sensor is wire bonded to a conductive layer of the substrate.

20 . The package of claim 18 , wherein the complementary metal-oxide-semiconductor image sensor includes a micro lens or filter assembly facing the transparent cover.

21 . The package of claim 18 , wherein the transparent cover includes an anti-reflective coating.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Hsieh Yu-Te

Classifications

• H10F39/8063

  Microlenses · CPC title

• H10F39/804 Primary

  Containers or encapsulations · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/011

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• H10F39/811 Primary

  Interconnections · CPC title