Finishing on packaging substrate with ultra high-density interconnects

Patent metadata

Field	Value
Publication number	US-2025279348-A1
Application number	US-202519064570-A
Country	US
Kind code	A1
Filing date	Feb 26, 2025
Priority date	Mar 1, 2024
Publication date	Sep 4, 2025
Grant date	—

Abstract

A packaging substrate is provided. The packaging substrate includes a core and first organic buildup layers on a first side of the core. The first organic buildup layers include an organic dielectric material and at least one of first metallic traces, first metallic vias, or first metallic pads. The packaging substrate includes second organic buildup layers on a second side of the core that is opposite the first side. The second organic buildup layers include the organic dielectric material and at least one of second metallic traces, second metallic vias, or second metallic pads. The packaging substrate includes first inorganic buildup layers disposed on the first organic buildup layers. The first inorganic buildup layers include an inorganic dielectric material and at least one of third metallic traces, third metallic vias, or third metallic pads.

First claim

What is claimed is:

1 . A packaging substrate, comprising:
a core; a one or more first organic buildup layers on a first side of the core, the one or more first organic buildup layers comprising an organic dielectric material and at least one of first metallic traces, first metallic vias, or first metallic pads; a one or more second organic buildup layers on a second side of the core that is opposite the first side, the one or more second organic buildup layers comprising the organic dielectric material and at least one of second metallic traces, second metallic vias, or second metallic pads; and one or more first inorganic buildup layers disposed on the one or more first organic buildup layers, the one or more first inorganic buildup layers comprising an inorganic dielectric material and at least one of third metallic traces, third metallic vias, or third metallic pads.

2 . The packaging substrate of claim 1 , wherein the one or more first organic buildup layers comprise metallic portions that protrude from an exterior-most surface of the organic dielectric material of the one or more first organic buildup layers.

3 . The packaging substrate of claim 1 , wherein the one or more first organic buildup layers comprise metallic portions that are planar with an exterior-most surface of the organic dielectric material of the one or more first organic buildup layers.

4 . The packaging substrate of claim 1 , wherein a distance between centers of adjacent metallic pads of the first metallic pads is at most 100 micrometers (μm).

5 . The packaging substrate of claim 1 , wherein a cross section of the first metallic pads of the one or more first organic buildup layers is about 1-30 micrometers (μm).

6 . The packaging substrate of claim 1 , wherein the inorganic dielectric material comprises at least one of silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).

7 . The packaging substrate of claim 1 , wherein the organic dielectric material comprises at least one of Ajinomoto buildup film (ABF) or polyimide.

8 . The packaging substrate of claim 1 , further comprising:
a one or more third organic buildup layers disposed on the one or more first inorganic build layers, the third one or more organic buildup layers comprising an organic dielectric material.

9 . The packaging substrate of claim 1 , wherein a distance between centers of adjacent metallic pads of the first metallic pads is about 5-50 micrometers (μm).

10 . The packaging substrate of claim 1 , wherein at least one of the one or more via structures is a blind via with a diameter at most 10 micrometers (μm), and wherein at least one of the one or more via structures is a through-assembly via with a diameter at most 30 μm.

11 . The packaging substrate of claim 1 , further comprising one or more second inorganic buildup layers disposed on the one or more second organic buildup layers, the one or more second inorganic buildup layers comprising the inorganic dielectric material and at least one of fourth metallic traces, fourth metallic vias, or fourth metallic pads.

12 . A method comprising:
depositing a first exterior layer comprising a first inorganic dielectric material onto a first side of a packaging substrate comprising a core and one or more interior layers on the first side, the one or more interior layers comprising a first organic dielectric material and a plurality of conductive traces; removing portions of the first exterior layer to form structures exposing portions of the plurality of conductive traces; depositing conductive material within the structures of the first exterior layer to form at least one of a plurality of vias or a plurality of fine traces electrically connected to the plurality of conductive traces; depositing a second exterior layer comprising a second inorganic dielectric material onto the first exterior layer; removing at least a portion of the second exterior layer to form structures exposing portions of the plurality of vias; and depositing conductive material within the structures of the second exterior layer to form a plurality of contact pads configured to electrically connect the packaging substrate to an integrated circuit.

13 . The method of claim 12 , wherein a distance between centers of adjacent contact pads of the plurality of contact pads is at most 20 micrometers (μm).

14 . The method of claim 12 , wherein a cross section of the plurality of contact pads is about 5-20 micrometers (μm).

15 . The method of claim 12 , wherein the first inorganic dielectric material comprises silicon dioxide (SiO 2 ) and wherein removing portions of the first exterior layer comprises employing at least one of photoresist application, photolithography, chemical etching, or plasma etching to the first exterior layer.

16 . The method of claim 12 , wherein the core is a silicon core.

17 . The method of claim 12 , wherein a distance between centers of adjacent contact pads of the plurality of contact pads is about 5-20 micrometers (μm).

18 . A system, comprising:
a packaging substrate; an integrated chip (IC) conductively connected to a first side of the packaging substrate; and a printed circuit board (PCB) conductively connected to a second side of the packaging substrate, wherein the packaging substrate comprises:
a core;
a one or more first organic buildup layers on a first side of the core, the one or more first organic buildup layers comprising an organic dielectric material and at least one of first metallic traces, first metallic vias, or first metallic pads;
a one or more second organic buildup layers on a second side of the core that is opposite the first side, the one or more second organic buildup layers comprising the organic dielectric material and at least one of second metallic traces, second metallic vias, or second metallic pads; and
one or more first inorganic buildup layers disposed on the one or more first organic buildup layers, the one or more first inorganic buildup layers comprising an inorganic dielectric material and at least one of third metallic traces, third metallic vias, or third metallic pads.

19 . The system of claim 18 , wherein the one or more first organic buildup layers comprise metallic portions that are planar with an exterior-most surface of the organic dielectric material of the one or more first organic buildup layers.

20 . The system of claim 18 , further comprising one or more second inorganic buildup layers disposed on the one or more second organic buildup layers, the one or more second inorganic buildup layers comprising the inorganic dielectric material and at least one of fourth metallic traces, fourth metallic vias, or fourth metallic pads.

Assignees

• Applied Materials Inc

Inventors

• Verhaverbeke Steven
• Chen Han-Wen
• Park Giback
• Zheng Kai
• Leschkies Kurtis Siegfried
• Houk Roman
• Iyer Subramanian Srikanteswara
• Harish Vineeth

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title